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fdd9c635cb
Campaign close: HEVC decode bit-perfect on ampere
master
Markus Fritsche
2026-05-16 22:41:06 +00:00
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24272596cd
iter7 Phase 0: pivot to cache-coherency hypothesis (H1) for iter5 black-output
Markus Fritsche
2026-05-16 22:32:20 +00:00
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b8930df801
iter6 v6 substrate: source-trace points NULL deref at 0x20 to dma_fence->context
Markus Fritsche
2026-05-16 22:29:57 +00:00
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9050b454a4
iter6 v3: stage KCSAN-only config delta script for second-pass build
Markus Fritsche
2026-05-16 19:36:24 +00:00
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96e2d439c9
iter6 v3 plan: apply Sonnet round-3 amendments
Markus Fritsche
2026-05-16 19:28:19 +00:00
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2de6870cb4
iter6 v3 plan: KASAN+KCSAN delta on lockdep substrate
Markus Fritsche
2026-05-16 19:26:55 +00:00
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53e247724f
iter6 v2 attempt-2 close — 0004 headless-clean but compositor-wedges
Markus Fritsche
2026-05-16 19:26:30 +00:00
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1656f84a40
iter6 plan v2: log A5 execution deviation — PROVE_RCU forced =y by kconfig
Markus Fritsche
2026-05-16 16:54:38 +00:00
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a8d563a917
iter6 plan v2: ramoops amendments (user chose ramoops over serial)
Markus Fritsche
2026-05-16 16:53:14 +00:00
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543bed905f
iter6 plan v2: add remote-operator DEFAULT override note (Sonnet round 2 Q3)
Markus Fritsche
2026-05-16 16:35:16 +00:00
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b02baffca7
iter6 post-mortem Phase 4 v2: per-codec 0007 + lockdep base kernel
Markus Fritsche
2026-05-16 16:33:08 +00:00
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0ef64406b6
iter6 post-mortem Phase 4: bisect-apply plan with lockdep base kernel
Markus Fritsche
2026-05-16 16:13:48 +00:00
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11d2dde8ab
iter6 post-mortem Phase 0: substrate + safeguards
Markus Fritsche
2026-05-16 16:02:09 +00:00
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1594def84e
iter5 close — HW reports DEC_RDY but CAPTURE is uniform black
Markus Fritsche
2026-05-16 11:43:59 +00:00
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46c956bd51
iter4 close — second kernel bug: missing HEVC_SLICE_PARAMS registration
Markus Fritsche
2026-05-16 11:18:04 +00:00
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0a400b6f08
iter4 Phase 0: HEVC per-frame S_EXT_CTRLS EINVAL substrate
Markus Fritsche
2026-05-16 11:14:41 +00:00
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659c08c81c
iter3 close — kernel root cause: uninitialized run.ext_sps_st_rps
Markus Fritsche
2026-05-16 10:34:13 +00:00
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dfebd8017f
iter3 phase0: HEVC kernel-side investigation substrate
marfrit
2026-05-16 09:48:57 +00:00
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17aa443f8f
iter2 close: F1 falsifier fired, mechanism reconstruction was wrong
marfrit
2026-05-16 09:31:24 +00:00
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d2ff661554
iter2 phase5: second-model review, 1 finding rebut, 3 findings adopt
marfrit
2026-05-16 08:57:06 +00:00
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a575e37190
iter2 phase4: concrete implementation plan for Phase 6
marfrit
2026-05-16 08:48:48 +00:00
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f5e681caf5
iter2 phase3: HEVC BEFORE-state baseline
marfrit
2026-05-16 08:48:12 +00:00
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5541e01d26
iter2 phase2: vendoring spec concrete + dependency chain re-verified
marfrit
2026-05-16 08:42:07 +00:00
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eefc378d93
iter2 phase1: HEVC backend extension goal + vendoring spec
marfrit
2026-05-16 08:41:22 +00:00
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299e376d51
iter2 phase0 update: upstream-consumer survey closes Q1 + Q2
marfrit
2026-05-16 08:38:52 +00:00
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cd047a34de
iter2 phase0: HEVC backend extension substrate
marfrit
2026-05-16 08:33:50 +00:00
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0b3c23ba66
meta-iter1 close: consolidated phases 2-8 with rationale
marfrit
2026-05-16 08:32:33 +00:00
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c46e025b2e
iter1 phase1: lock meta-campaign goal + sub-iteration ledger
marfrit
2026-05-16 08:32:06 +00:00
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2a5f5c296e
iter1 phase0: substrate + prior-art survey (HEVC reclassified)
marfrit
2026-05-16 08:10:40 +00:00
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72f658d7b9
scaffold: kernel-side sibling campaign for RK3588 decoder enablement
marfrit
2026-05-16 08:07:55 +00:00