Phase 1 v1 claimed VP9 enablement was a < 100-line wiring patch
reusing legacy rkvdec_vp9_fmt_ops in vdpu381_coded_fmts[]. Janet
architect review (verdict AMEND) surfaced two BLOCKERs that overturn
the thesis:
A. vdpu381_variant.num_regs is unset (defaults 0); legacy VP9 path's
rkvdec_memcpy_toio writes MIN(sizeof, 0)=0 bytes. Zero MMIO config.
B. vdpu381 register layout is segmented across 5 distinct OFFSET_*
blocks (COMMON, CODEC_PARAMS, COMMON_ADDR, CODEC_ADDR, POC_HIGHBIT)
plus decode trigger at VDPU381_REG_DEC_E=0x028. Legacy VP9 writes
flat-from-base+0 and triggers via RKVDEC_REG_INTERRUPT=0x004 —
wrong register-block layout AND wrong trigger offset.
Plus Amendment C: BSP rkvdec2_irq checks BIT(1); mainline
vdpu381_irq_handler checks BIT(2). Same register (0x380), different
bit. VP9-set BIT(1) status would misclassify as ERROR.
Both blockers confirmed empirically by reading mainline rkvdec.c and
BSP mpp_rkvdec2.c source (rkvdec2_run dispatches via mpp_write_req
on req->offset, NOT a flat dump; trans_tbl_vp9d shares HEVC's
128..199 register-DMA range).
v2 architecture: new rkvdec-vdpu381-vp9.c backend (~600-800 lines)
+ extracted rkvdec-vp9-common.{c,h} for the SPEC layer (probability
tables, frame_ctx, segmap) + VP9 register-struct extensions in
rkvdec-vdpu381-regs.h. Reuses vdpu381_irq_handler, V4L2 controls,
RCB infrastructure, IOMMU path — all confirmed as codec-agnostic.
Sourcing the bit-packed register struct definitions from Rockchip
BSP MPP hal_vp9d_vdpu382.c (vdpu382 = sibling IP family).
Next: Phase 1 v2 → Janet re-review for sign-off before Phase 2 code.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
