Path B pivot + Phase 0-3 closed with first baseline numbers
This is a from-scratch initial commit on a fresh .git. The original
scaffold commit (7510b56) and the earlier session's working-tree
docs were lost in a 2026-05-18 10:25 working-tree wipe; the corrupted
.git is preserved at .git-broken-2026-05-18/ (gitignored) for
forensic inspection.
Scope re-anchored from Path A (custom VPU firmware on VC7 scalar
cores; blocked by BCM2712 silicon-RoT mask-ROM signature check)
to Path B (QPU compute kernels via Mesa v3d / Vulkan compute or
direct DRM, on stock signed Pi 5 / CM5). See README.md and
docs/phase0.md for the substrate audit that closed Path A.
Phases closed:
Phase 0 — substrate audit; Path A blocked, Path B open;
codec-back-end-fits-QPU finding (docs/phase0.md)
Phase 1 — first kernel locked (VP9 / AV1 8x8 inverse DCT) with
publish-before-measure R = M2/M3 decision rules
(docs/phase1.md)
Phase 2 — reference impls mapped; FFmpeg n7.1.3 source vendored
under external/ffmpeg-snapshot/ (PROVENANCE.md pins
commit f46e514 + per-file SHA-256s) (docs/phase2.md)
Phase 3 — real baseline measurements on hertz (docs/phase3.md):
M1 bit-exact 100.0000 % (10000/10000)
M3 NEON IDCT8 single 8.171 Mblock/s (122.4 ns/block)
M5a empty Vulkan submit 22.66 us
M5b 1-WG noop dispatch 55.60 us
M5 delta 32.95 us/dispatch
=> per-dispatch overhead is ~455x per-NEON-block cost;
Phase 4 must batch at frame level or close to it.
Build harness in place: CMakeLists.txt + tests/{bench_neon_idct.c,
vp9_idct8_ref.c, bench_vulkan_dispatch.c, shaders/noop.comp} +
external/ffmpeg-snapshot/config.h shim (7 defines + EXTERN_ASM).
Builds clean on Debian Trixie aarch64 with cmake 3.31, ninja 1.12,
libvulkan-dev 1.4.309, glslang-tools 15.1.0. Vendored FFmpeg .S
assembles via the config.h shim.
Next: Phase 4 (plan first QPU IDCT kernel under the M5 batching
constraint) -> Phase 5 second-model review -> Phase 6 implement.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
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# daedalus-fourier
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Community-built VP9 / AV1 software-decode back-end running on the
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VideoCore VII (V3D 7.1) QPUs on Broadcom BCM2712 (Raspberry Pi 5 /
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Compute Module 5), via the existing Mesa `v3d` userspace driver.
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ARM keeps the serial entropy front-end; the QPU takes the parallel
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back-end (inverse transforms, deblocking, CDEF, loop restoration,
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MC residual add).
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> Daedalus built the Labyrinth for King Minos, then escaped from it
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> by hand-forging flight firmware out of feathers and wax when no
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> sanctioned exit existed.
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That's the project shape. The Broadcom-locked VideoCore VII is the
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Labyrinth; the Pi Foundation's "use the HEVC block and live with
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software decode for everything else" is the official non-exit;
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the QPU sits unused inside the labyrinth's walls.
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**Status: Phase 0 closed (substrate audit). Phase 1 in progress
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(first-kernel proof on hertz).** This is research-track work that
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may take months or may yield a single proof-of-concept kernel that
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loses to ARM NEON, in which case the negative result ships and the
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project closes.
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## Why this exists
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higgs is a Raspberry Pi Compute Module 5 in a small portable
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chassis with a battery. Watching nerds review *Star Wars* on YouTube
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while putting Mac Studios into virtual shopping baskets is a
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core workload for the higgs class of device.
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YouTube serves H.264 (legacy), VP9 (typical 4K), and AV1 (newer
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high-bitrate / high-resolution content). It does not serve HEVC.
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Pi 5's BCM2712 has one HW decoder block: HEVC. The intersection
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of {what YouTube serves} ∩ {what BCM2712 decodes in HW} = ∅.
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Every YouTube frame on higgs today is software-decoded on Cortex-A76
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cores at ~50–90% CPU per video stream. Offloading the parallel
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back-end of that decode to the otherwise-idle QPU complex *might*
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recover meaningful CPU time and battery on higgs. The honest
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prior — measured in Phase 0 — is that the QPU has roughly equal
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raw compute to the A76 cluster but a smaller slice of the shared
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LPDDR4x bandwidth, so the win, if any, comes from offloading
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*concurrent* work the CPU would have done anyway.
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The Pi Foundation isn't going to do this work (per their own
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statement: chromium-patch sustainment was too much; codec
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sustainment would be moreso). The kernel `rpi-hevc-dec` series has
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been 17 months in review for one decoder block they DID write
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themselves. Whatever ships here ships through the community.
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## Architecture (Path B)
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Phase 0 closed two paths:
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- **Path A — custom VPU firmware on the VC7 scalar cores.**
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Blocked. BCM2712 has a silicon root of trust: the mask ROM
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hardcodes RPi's public key and unconditionally verifies the
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second-stage bootloader. `EXECUTE_CODE` mailbox removed on Pi 5.
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No software-only bypass exists. See `docs/phase0.md §3`.
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- **Path B — QPU compute kernels via the existing Mesa `v3d` /
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DRM / Vulkan-compute path.** This is the path. The QPU is
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reachable from userspace today on a stock signed Pi 5 / CM5
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via `/dev/dri/card0`. No firmware loading. No signing fight.
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`Idein/py-videocore7` (SGEMM 21 GFLOPS sustained) is the
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existence proof.
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The build:
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```
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┌───────────────────────────────┐
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│ userspace VP9 / AV1 decoder │
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│ (fork of dav1d / libvpx) │
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├───────────────────────────────┤
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│ ARM: entropy decode │ ← Cortex-A76 + NEON
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│ (Bool coder / ANS) │ structurally serial
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├───────────────────────────────┤
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│ QPU: parallel back-end │ ← V3D 7.1 via Mesa v3dv
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│ (IDCT, CDEF, │ Vulkan compute shaders
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│ deblock, LR, MC) │ or direct DRM submit
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├───────────────────────────────┤
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│ V4L2 stateless wrapper │ ← out-of-tree kernel module
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│ (eventual, kernel-agent) │ exposing /dev/videoN
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└───────────────────────────────┘
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```
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The first deliverable is *not* the V4L2 wrapper. The first
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deliverable is one back-end kernel running on the QPU, bit-exact
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against a libavcodec reference, with measured throughput. If that
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single kernel can't beat NEON or get within 50% of it, the project
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closes here with a documented negative result.
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## In scope
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- A small set of codec back-end kernels (IDCT 8×8, CDEF, deblocking,
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loop restoration filter, MC interpolation) compiled as SPIR-V
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compute shaders for Mesa `v3dv`, dispatched via Vulkan compute
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from userspace.
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- A test harness on hertz that runs each kernel against libavcodec
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reference outputs and measures throughput (megapixels/sec or
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blocks/sec) against the equivalent NEON path.
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- Phase 1 = one kernel, bit-exact, with numbers. Phase 2+ = more
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kernels only if Phase 1 numbers justify it.
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## Out of scope (for now)
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- HEVC (Pi 5 has dedicated silicon; `rpi-hevc-dec` covers it).
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- Pi 4 / BCM2711 / VideoCore VI. Different ISA, smaller compute
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budget. Path B *could* extend but isn't the priority.
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- Encode. Pi Foundation removed all HW encode in Pi 5; encode on
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VC7 is a separate, larger project.
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- Custom VPU firmware (Path A — blocked by silicon RoT, see
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`docs/phase0.md`).
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- V4L2 stateless driver wrapping the userspace decoder. Eventual
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consumption point, but Phase 1 lives entirely in userspace.
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- Beating ARM NEON unconditionally. The honest target is
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*concurrent* work: QPU runs while CPU does something else.
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## Dev substrate
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- **hertz** (Pi 5, 8 GB, Debian Trixie, kernel 6.12.75-rpt-rpi-2712,
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Mesa 25.0.7 with v3dv, V3D 7.1.7) — the dev / test / measurement
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host. Watchdog-protected for crash recovery. See
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`docs/vulkaninfo_v3d_7_1_7_hertz.txt` for the inside-view device
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profile.
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- **higgs** (CM5 in portable battery chassis) — the eventual user
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target. Not a dev unit; sealed chassis.
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## Conventions
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This project follows the 9(+1)-phase dev process. See
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`docs/dev_process.md`. Phase 0 is closed (`docs/phase0.md`);
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Phase 1 is `docs/phase1.md`.
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Gitea identity: `claude-noether` (per
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`feedback_gitea_as_claude_noether.md`). No `marfrit` pushes from
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Claude sessions.
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## Layout
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```
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daedalus-fourier/
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├── README.md ← this file
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├── docs/
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│ ├── dev_process.md ← reference copy of the 9(+1)-phase loop
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│ ├── phase0.md ← substrate audit (closes Paths A and B)
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│ ├── phase1.md ← first-kernel goal + measurement plan
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│ └── vulkaninfo_v3d_7_1_7_hertz.txt
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│ ← inside-view device profile from hertz
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├── src/ ← kernels + Vulkan dispatch harness
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└── tests/ ← bit-exact vs libavcodec, throughput
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```
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No build system yet. Adding CMake when the first kernel lands.
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## Sibling projects in the same orbit
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- `libva-v4l2-request-fourier` — VA-API consumer-side backend.
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Eventual consumer if daedalus produces a V4L2 stateless node.
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- `firefox-fourier` — Firefox fork that routes stateless V4L2
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through libavcodec's `v4l2_request` hwaccel. Same pickup point.
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- `chromium-fourier` — sibling for Chromium.
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- `kernel-agent` — would house the V4L2 driver wrapping the
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userspace decoder, once one exists.
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- `ampere-av1-enablement` — software-side AV1 bring-up on RK3588
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(rkvdec / vpu981). Provides the userspace conformance harness
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daedalus reuses for VC7-AV1 verification.
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## Source attribution
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Daedalus-the-myth is public domain. The wax-and-feathers
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metaphor is older than software engineering.
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Anyone wanting to fail at this project: please file your failures
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under `branches/icarus/`. Built-in self-deprecation slot, with
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honor.
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