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460a6a6d08
Calibration: M4 same-kernel measures worst-case contention
main
marfrit
2026-05-18 13:31:27 +00:00
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20b59cd6a5
Cycle 5 phase 3 partial: M3 NEON = 3.923 Mblock/s; M1 deferred
marfrit
2026-05-18 13:21:24 +00:00
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2cd2258a7b
Cycle 5 setup (Phase 1+2): vendor dav1d 1.4.3 CDEF sources
marfrit
2026-05-18 13:12:25 +00:00
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20e3d004ae
Issues 001+002: defer LPF wd=16 + LPF vertical variants
marfrit
2026-05-18 13:09:51 +00:00
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85feba4087
Cycle 4 (LPF wd=8) closure: M1=100%, R=0.34, M4=+4.1%, PASS
marfrit
2026-05-18 12:56:25 +00:00
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356e446a49
Cycle 3 (MC interpolation) closure: M1'''=100%, R'''=0.067 RED, M4=-19.5%
marfrit
2026-05-18 12:51:43 +00:00
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36eca40ff2
Cycle 2 (LPF) closure: M1''=100%, R''=0.41, M4''=+6.9%, PASS
marfrit
2026-05-18 12:39:26 +00:00
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be7ff5587c
Cycle 2 (deblocking) Phase 1-3: M3'' = 48.285 Medge/s baseline
marfrit
2026-05-18 12:28:57 +00:00
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8182e43c15
Phase 7 M4: mixed CPU+QPU beats pure 4-core NEON; project continues
marfrit
2026-05-18 12:18:36 +00:00
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d66f22f333
Phase 6 (v1+v4 production) + Phase 7 closure: R = 0.92 ± 0.03 on hertz
marfrit
2026-05-18 12:09:00 +00:00
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71db72928f
Phase 4 plan + Phase 5 second-model review (PASS-WITH-REVISIONS)
marfrit
2026-05-18 11:47:03 +00:00
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dcbbc77038
Path B pivot + Phase 0-3 closed with first baseline numbers
marfrit
2026-05-18 11:30:12 +00:00