Julian
ba20341e70
Source: https://github.com/cringeops/bes2600 Source: https://github.com/cringeops/bes2600/pull/14 Source: https://github.com/cringeops/bes2600/pull/17 Source: https://github.com/cringeops/bes2600/pull/20
301 lines
9.5 KiB
C
301 lines
9.5 KiB
C
/*
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* Low-level API for mac80211 BES2600 drivers
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*
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* Copyright (c) 2010, Bestechnic
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* Author:
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*
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* Based on:
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* UMAC BES2600 driver which is
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* Copyright (c) 2010, Bestechnic
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* Author:
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef BES2600_HWIO_H_INCLUDED
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#define BES2600_HWIO_H_INCLUDED
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/* extern */ struct sbus_ops;
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/* extern */ struct sbus_priv;
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/* DPLL initial values */
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#define DPLL_INIT_VAL_9000 (0x00000191)
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#define DPLL_INIT_VAL_BES2600 (0x0EC4F121)
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/* Hardware Type Definitions */
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#define HIF_8601_VERSATILE (0)
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#define HIF_8601_SILICON (1)
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#define HIF_9000_SILICON_VERSTAILE (2)
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#define BES2600_CUT_11_ID_STR (0x302E3830)
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#define BES2600_CUT_22_ID_STR1 (0x302e3132)
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#define BES2600_CUT_22_ID_STR2 (0x32302e30)
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#define BES2600_CUT_22_ID_STR3 (0x3335)
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#define CW1250_CUT_11_ID_STR1 (0x302e3033)
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#define CW1250_CUT_11_ID_STR2 (0x33302e32)
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#define CW1250_CUT_11_ID_STR3 (0x3535)
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#define BES2600_CUT_ID_ADDR (0xFFF17F90)
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#define BES2600_CUT2_ID_ADDR (0xFFF1FF90)
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/* Download control area */
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/* boot loader start address in SRAM */
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#define DOWNLOAD_BOOT_LOADER_OFFSET (0x00000000)
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/* 32K, 0x4000 to 0xDFFF */
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#define DOWNLOAD_FIFO_OFFSET (0x00004000)
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/* 32K */
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#define DOWNLOAD_FIFO_SIZE (0x00008000)
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/* 128 bytes, 0xFF80 to 0xFFFF */
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#define DOWNLOAD_CTRL_OFFSET (0x0000FF80)
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#define DOWNLOAD_CTRL_DATA_DWORDS (32-6)
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struct download_cntl_t {
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/* size of whole firmware file (including Cheksum), host init */
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u32 ImageSize;
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/* downloading flags */
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u32 Flags;
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/* No. of bytes put into the download, init & updated by host */
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u32 Put;
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/* last traced program counter, last ARM reg_pc */
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u32 TracePc;
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/* No. of bytes read from the download, host init, device updates */
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u32 Get;
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/* r0, boot losader status, host init to pending, device updates */
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u32 Status;
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/* Extra debug info, r1 to r14 if status=r0=DOWNLOAD_EXCEPTION */
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u32 DebugData[DOWNLOAD_CTRL_DATA_DWORDS];
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};
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#define DOWNLOAD_IMAGE_SIZE_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, ImageSize))
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#define DOWNLOAD_FLAGS_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Flags))
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#define DOWNLOAD_PUT_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Put))
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#define DOWNLOAD_TRACE_PC_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, TracePc))
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#define DOWNLOAD_GET_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Get))
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#define DOWNLOAD_STATUS_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Status))
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#define DOWNLOAD_DEBUG_DATA_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, DebugData))
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#define DOWNLOAD_DEBUG_DATA_LEN (108)
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#define DOWNLOAD_BLOCK_SIZE (1024)
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/* For boot loader detection */
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#define DOWNLOAD_ARE_YOU_HERE (0x87654321)
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#define DOWNLOAD_I_AM_HERE (0x12345678)
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/* Download error code */
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#define DOWNLOAD_PENDING (0xFFFFFFFF)
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#define DOWNLOAD_SUCCESS (0)
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#define DOWNLOAD_EXCEPTION (1)
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#define DOWNLOAD_ERR_MEM_1 (2)
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#define DOWNLOAD_ERR_MEM_2 (3)
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#define DOWNLOAD_ERR_SOFTWARE (4)
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#define DOWNLOAD_ERR_FILE_SIZE (5)
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#define DOWNLOAD_ERR_CHECKSUM (6)
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#define DOWNLOAD_ERR_OVERFLOW (7)
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#define DOWNLOAD_ERR_IMAGE (8)
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#define DOWNLOAD_ERR_HOST (9)
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#define DOWNLOAD_ERR_ABORT (10)
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#define SYS_BASE_ADDR_SILICON (0)
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#define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
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#define PAC_SHARED_MEMORY_SILICON (PAC_BASE_ADDRESS_SILICON)
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#define BES26000_APB(addr) (PAC_SHARED_MEMORY_SILICON + (addr))
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/* ***************************************************************
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*Device register definitions
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*************************************************************** */
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/* WBF - SPI Register Addresses */
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#define ST90TDS_ADDR_ID_BASE (0x0000)
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/* 16/32 bits */
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#define ST90TDS_CONFIG_REG_ID (0x0000)
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/* 16/32 bits */
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#define ST90TDS_CONTROL_REG_ID (0x0001)
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/* 16 bits, Q mode W/R */
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#define ST90TDS_IN_OUT_QUEUE_REG_ID (0x0002)
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/* 32 bits, AHB bus R/W */
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#define ST90TDS_AHB_DPORT_REG_ID (0x0003)
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/* 16/32 bits */
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#define ST90TDS_SRAM_BASE_ADDR_REG_ID (0x0004)
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/* 32 bits, APB bus R/W */
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#define ST90TDS_SRAM_DPORT_REG_ID (0x0005)
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/* 32 bits, t_settle/general */
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#define ST90TDS_TSET_GEN_R_W_REG_ID (0x0006)
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/* 16 bits, Q mode read, no length */
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#define ST90TDS_FRAME_OUT_REG_ID (0x0007)
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#define ST90TDS_ADDR_ID_MAX (ST90TDS_FRAME_OUT_REG_ID)
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/* WBF - Control register bit set */
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/* next o/p length, bit 11 to 0 */
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#define ST90TDS_CONT_NEXT_LEN_MASK (0x0FFF)
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#define ST90TDS_CONT_WUP_BIT (BIT(12))
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#define ST90TDS_CONT_RDY_BIT (BIT(13))
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#define ST90TDS_CONT_IRQ_ENABLE (BIT(14))
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#define ST90TDS_CONT_RDY_ENABLE (BIT(15))
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#define ST90TDS_CONT_IRQ_RDY_ENABLE (BIT(14)|BIT(15))
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/* SPI Config register bit set */
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#define ST90TDS_CONFIG_FRAME_BIT (BIT(2))
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#define ST90TDS_CONFIG_WORD_MODE_BITS (BIT(3)|BIT(4))
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#define ST90TDS_CONFIG_WORD_MODE_1 (BIT(3))
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#define ST90TDS_CONFIG_WORD_MODE_2 (BIT(4))
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#define ST90TDS_CONFIG_ERROR_0_BIT (BIT(5))
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#define ST90TDS_CONFIG_ERROR_1_BIT (BIT(6))
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#define ST90TDS_CONFIG_ERROR_2_BIT (BIT(7))
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/* TBD: Sure??? */
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#define ST90TDS_CONFIG_CSN_FRAME_BIT (BIT(7))
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#define ST90TDS_CONFIG_ERROR_3_BIT (BIT(8))
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#define ST90TDS_CONFIG_ERROR_4_BIT (BIT(9))
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/* QueueM */
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#define ST90TDS_CONFIG_ACCESS_MODE_BIT (BIT(10))
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/* AHB bus */
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#define ST90TDS_CONFIG_AHB_PFETCH_BIT (BIT(11))
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#define ST90TDS_CONFIG_CPU_CLK_DIS_BIT (BIT(12))
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/* APB bus */
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#define ST90TDS_CONFIG_PFETCH_BIT (BIT(13))
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/* cpu reset */
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#define ST90TDS_CONFIG_CPU_RESET_BIT (BIT(14))
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#define ST90TDS_CONFIG_CLEAR_INT_BIT (BIT(15))
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/* For BES2600 the IRQ Enable and Ready Bits are in CONFIG register */
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#define ST90TDS_CONF_IRQ_RDY_ENABLE (BIT(16)|BIT(17))
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void bes2600_reg_set_object(struct sbus_ops *ops, struct sbus_priv *priv);
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int bes2600_data_read(void *buf, size_t buf_len);
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int bes2600_data_write(const void *buf, size_t buf_len);
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int bes2600_reg_read(u32 addr, void *buf, size_t buf_len);
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int bes2600_reg_write(u32 addr, const void *buf, size_t buf_len);
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static inline int bes2600_reg_read_16(u16 addr, u16 *val)
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{
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return bes2600_reg_read(addr, val, sizeof(*val));
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}
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static inline int bes2600_reg_write_16(u16 addr, u16 val)
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{
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return bes2600_reg_write(addr, &val, sizeof(val));
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}
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static inline int bes2600_reg_read_32(u16 addr, u32 *val)
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{
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return bes2600_reg_read(addr, val, sizeof(val));
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}
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static inline int bes2600_reg_write_32(u16 addr, u32 val)
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{
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return bes2600_reg_write(addr, &val, sizeof(val));
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}
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int bes2600_indirect_read(u32 addr, void *buf, size_t buf_len, u32 prefetch, u16 port_addr);
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int bes2600_apb_write(u32 addr, const void *buf, size_t buf_len);
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int bes2600_ahb_write(u32 addr, const void *buf, size_t buf_len);
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static inline int bes2600_apb_read(u32 addr, void *buf, size_t buf_len)
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{
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return bes2600_indirect_read(addr, buf, buf_len,
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ST90TDS_CONFIG_PFETCH_BIT, ST90TDS_SRAM_DPORT_REG_ID);
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}
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static inline int bes2600_ahb_read(u32 addr, void *buf, size_t buf_len)
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{
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return bes2600_indirect_read(addr, buf, buf_len,
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ST90TDS_CONFIG_AHB_PFETCH_BIT, ST90TDS_AHB_DPORT_REG_ID);
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}
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static inline int bes2600_apb_read_32(u32 addr, u32 *val)
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{
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return bes2600_apb_read(addr, val, sizeof(val));
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}
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static inline int bes2600_apb_write_32(u32 addr, u32 val)
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{
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return bes2600_apb_write(addr, &val, sizeof(val));
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}
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static inline int bes2600_ahb_read_32(u32 addr, u32 *val)
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{
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return bes2600_ahb_read(addr, val, sizeof(val));
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}
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#if defined(BES2600_DETECTION_LOGIC)
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static inline int bes2600_ahb_write_32(u32 addr, u32 val)
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{
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return bes2600_ahb_write(addr, &val, sizeof(val));
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}
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#endif /*BES2600_DETECTION_LOGIC*/
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#ifdef CONFIG_BES2600_WLAN_USB
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#define BES_TX_DATA_ADDR (0x0)
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#endif
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#define SDIO_DEVICE_SEND_INT_LEN_SEPARATE
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#define BES_TX_CTRL_REG_ID (0x0)
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#ifdef SDIO_DEVICE_SEND_INT_LEN_SEPARATE
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#define BES_TX_NEXT_LEN_REG_ID (0x104)
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#else
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#define BES_TX_NEXT_LEN_REG_ID BES_TX_CTRL_REG_ID
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#endif
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#define BES_TX_NEXT_LEN_MASK (0xffff)
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#define BES_TX_DATA_ADDR (0x0)
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#define BES_HOST_INT_REG_ID (0x120)
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#define BES_HOST_INT (1 << 0)
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#define BES_AP_WAKEUP_CFG (1 << 1)
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#define BES_SUBSYSTEM_MCU_DEACTIVE (1 << 2)
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#define BES_SUBSYSTEM_MCU_ACTIVE (1 << 3)
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#define BES_SUBSYSTEM_WIFI_DEACTIVE (1 << 4)
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#define BES_SUBSYSTEM_WIFI_ACTIVE (1 << 5)
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#define BES_SUBSYSTEM_WIFI_DEBUG (1 << 6)
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#define BES_SUBSYSTEM_BT_DEACTIVE (1 << 7)
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#define BES_SUBSYSTEM_BT_ACTIVE (1 << 8)
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#define BES_SUBSYSTEM_SYSTEM_CLOSE (1 << 9)
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#define BES_SUBSYSTEM_BT_WAKEUP (1 << 10)
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#define BES_SUBSYSTEM_BT_SLEEP (1 << 11)
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#define BES_AP_WAKEUP_TYPE_MASK 0xC
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#define BES_AP_WAKEUP_TYPE_SHIFT 2
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#define BES_AP_WAKEUP_TYPE_GPIO 0
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#define BES_AP_WAKEUP_TYPE_IF 1
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#define BES_AP_WAKEUP_REG_ID (0x124)
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#define BES_AP_WAKEUP_CFG_VALID (0x80)
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#define BES_AP_WAKEUP_GPIO_MASK (0x3)
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#define BES_AP_WAKEUP_GPIO_HIGH (0x0)
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#define BES_AP_WAKEUP_GPIO_LOW (0x1)
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#define BES_AP_WAKEUP_GPIO_RISE (0x2)
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#define BES_AP_WAKEUP_GPIO_FALL (0x3)
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#define BES_SLAVE_STATUS_REG_ID (0x10c)
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#define BES_SLAVE_STATUS_MCU_READY (1 << 0)
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#define BES_SLAVE_STATUS_DPD_READY (1 << 1)
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#define BES_SLAVE_STATUS_WIFI_READY (1 << 2)
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#define BES_SLAVE_STATUS_BT_READY (1 << 3)
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#define BES_SLAVE_STATUS_MCU_WAKEUP_READY (1 << 4)
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#define BES_SLAVE_STATUS_BT_WAKE_READY (1 << 5)
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#define BES_SLAVE_STATUS_DPD_LOG_READY (1 << 6)
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#define PACKET_TOTAL_LEN(len) ((len) & 0xffff)
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#define PACKET_COUNT(len) (((len) >> 16) & 0xff)
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#define PAKCET_CRC8(len) (((len) >> 24) & 0xff)
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#define BES_SDIO_RX_MULTIPLE_NUM (16)
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#define BES_SDIO_TX_MULTIPLE_NUM (16)
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#define BES_SDIO_TX_MULTIPLE_NUM_NOSIGNAL (1)
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#define MAX_SDIO_TRANSFER_LEN (32768)
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#endif /* BES2600_HWIO_H_INCLUDED */
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