h264: V3D shader for deblock_luma_h — first QPU port since cycle 9

Ports cycle 8's v3d_h264deblock.comp (V edge, horizontal across a row)
to the H orientation (V edge, horizontal across a column).  Same
algorithm, transposed access pattern:

  V variant: lane → column, reads/writes pix[±N*stride] (vertical I/O)
  H variant: lane → row,    reads/writes pix[±N]        (horizontal I/O)

  WG geometry unchanged: 256 invocations, 16 edges/WG, 16 lanes/edge.
  Lane-in-edge interpretation flips: column-index for V → row-index
  for H.  tc0 segment math unchanged (one tc0 byte per 4 lanes).
  dst_max calculation flips: V used dst_off + 3*stride + 16 (cols),
  H uses dst_off + 15*stride + 4 (rows).

Recipe table: DAEDALUS_KERNEL_H264_DEBLOCK_LH = QPU (was CPU).  AUTO
dispatch now picks QPU for the H edge as well as the V edge.  CPU
NEON path stays as the explicit-SUBSTRATE_CPU + has_qpu=0 fallback.

Verified on hertz (Pi 5 / V3D 7.1):

  $ ./build/test_api_h264 | grep luma_h
    H264_DEBLOCK_LH recipe substrate: 2     (was 1 — flipped to QPU)
    H.264 deblock luma h: 1024/1024 bytes bit-exact (100.0000%)

Bit-exact against the C reference (h264_h_loop_filter_luma_ref) on
8 tiles × 8 cols × 16 rows of random input.  Same correctness gate
as the cycle 8 V shader.

CMake plumbing: glslang rule for v3d_h264deblock_h.comp; new SPV
added to daedalus_shaders ALL list + install rule.  daedalus_ctx
gains a parallel h264deblock_h_pipe_ready / h264deblock_h_pipe pair
(can't share with V because pipelines bind a specific SPIR-V module
at create time).

What this changes for the substitution arc: PR #97's 0008-h264-
deblock-luma-h substitution patch already plumbed
daedalus_recipe_dispatch_h264_deblock_luma_h through libavcodec.
That path was NEON-by-recipe; with this PR it becomes QPU-by-recipe
(unless the libavcodec ctx is no-QPU per daedalus_ctx_create_no_qpu,
in which case it stays NEON — same shape as cycle 8's V shader).

Coverage state for H.264 8-bit 4:2:0 deblock kernels (QPU shaders):
  luma_v       ✓ cycle 8       ✓ now
  luma_h       —               ✓ THIS PR
  chroma_v/h   —               (CPU NEON; smaller tiles, lower-priority)
  *_intra (4)  —               (CPU NEON; less common)

CMakeLists.txt

@@ -284,6 +284,17 @@ if (DAEDALUS_BUILD_VULKAN)
         VERBATIM
     )
 
+    set(H264DEBLOCK_H_SPV ${CMAKE_BINARY_DIR}/v3d_h264deblock_h.spv)
+    add_custom_command(
+        OUTPUT ${H264DEBLOCK_H_SPV}
+        COMMAND ${GLSLANG_VALIDATOR} -V --target-env vulkan1.3
+                -o ${H264DEBLOCK_H_SPV}
+                ${CMAKE_SOURCE_DIR}/src/v3d_h264deblock_h.comp
+        DEPENDS ${CMAKE_SOURCE_DIR}/src/v3d_h264deblock_h.comp
+        COMMENT "glslang: v3d_h264deblock_h.comp -> v3d_h264deblock_h.spv"
+        VERBATIM
+    )
+
     set(H264_IDCT4_SPV ${CMAKE_BINARY_DIR}/v3d_h264_idct4.spv)
     add_custom_command(
         OUTPUT ${H264_IDCT4_SPV}
@@ -317,7 +328,7 @@ if (DAEDALUS_BUILD_VULKAN)
         VERBATIM
     )
 
-    add_custom_target(daedalus_shaders ALL DEPENDS ${NOOP_SPV} ${IDCT8_SPV} ${LPF_SPV} ${MC_SPV} ${LPF8_SPV} ${CDEF_SPV} ${H264DEBLOCK_SPV} ${H264_IDCT4_SPV} ${H264_IDCT8_SPV} ${H264_QPEL_MC20_SPV})
+    add_custom_target(daedalus_shaders ALL DEPENDS ${NOOP_SPV} ${IDCT8_SPV} ${LPF_SPV} ${MC_SPV} ${LPF8_SPV} ${CDEF_SPV} ${H264DEBLOCK_SPV} ${H264DEBLOCK_H_SPV} ${H264_IDCT4_SPV} ${H264_IDCT8_SPV} ${H264_QPEL_MC20_SPV})
 
     # v3d_runner — reusable Vulkan plumbing.
     add_library(v3d_runner STATIC src/v3d_runner.c)
@@ -450,6 +461,7 @@ if (DAEDALUS_BUILD_VULKAN)
         ${LPF8_SPV}
         ${CDEF_SPV}
         ${H264DEBLOCK_SPV}
+        ${H264DEBLOCK_H_SPV}
         ${H264_IDCT4_SPV}
         ${H264_IDCT8_SPV}
         ${H264_QPEL_MC20_SPV}

src/daedalus_core.c

@@ -40,6 +40,8 @@ struct daedalus_ctx {
     v3d_pipeline  cdef_pipe;
     int           h264deblock_pipe_ready;
     v3d_pipeline  h264deblock_pipe;
+    int           h264deblock_h_pipe_ready;
+    v3d_pipeline  h264deblock_h_pipe;
     int           h264_idct4_pipe_ready;
     v3d_pipeline  h264_idct4_pipe;
     int           h264_idct8_pipe_ready;
@@ -100,6 +102,7 @@ void daedalus_ctx_destroy(daedalus_ctx *ctx)
         if (ctx->mc8h_pipe_ready)        v3d_runner_destroy_pipeline(ctx->runner, &ctx->mc8h_pipe);
         if (ctx->cdef_pipe_ready)        v3d_runner_destroy_pipeline(ctx->runner, &ctx->cdef_pipe);
         if (ctx->h264deblock_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264deblock_pipe);
+        if (ctx->h264deblock_h_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264deblock_h_pipe);
         if (ctx->h264_idct4_pipe_ready)  v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_idct4_pipe);
         if (ctx->h264_idct8_pipe_ready)  v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_idct8_pipe);
         if (ctx->h264_qpel_mc20_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_qpel_mc20_pipe);
@@ -130,7 +133,7 @@ daedalus_substrate daedalus_recipe_substrate_for(daedalus_kernel k)
     case DAEDALUS_KERNEL_H264_IDCT4:       return DAEDALUS_SUBSTRATE_QPU;	/* v3d_h264_idct4.spv */
     case DAEDALUS_KERNEL_H264_IDCT8:       return DAEDALUS_SUBSTRATE_QPU;	/* v3d_h264_idct8.spv */
     case DAEDALUS_KERNEL_H264_DEBLOCK_LV:  return DAEDALUS_SUBSTRATE_QPU;	/* v3d_h264deblock.spv */
-    case DAEDALUS_KERNEL_H264_DEBLOCK_LH:  return DAEDALUS_SUBSTRATE_CPU;	/* QPU H shader pending */
+    case DAEDALUS_KERNEL_H264_DEBLOCK_LH:  return DAEDALUS_SUBSTRATE_QPU;	/* v3d_h264deblock_h.spv */
     case DAEDALUS_KERNEL_H264_DEBLOCK_CV:  return DAEDALUS_SUBSTRATE_CPU;	/* chroma QPU pending */
     case DAEDALUS_KERNEL_H264_DEBLOCK_CH:  return DAEDALUS_SUBSTRATE_CPU;	/* chroma QPU pending */
     case DAEDALUS_KERNEL_H264_DEBLOCK_LV_INTRA: return DAEDALUS_SUBSTRATE_CPU; /* bS=4 luma QPU pending */
@@ -1013,6 +1016,74 @@ fail:
     return -1;
 }
 
+/* -------------------- H.264 luma_h deblock QPU dispatch -------- */
+
+static int dispatch_h264_deblock_h_qpu(daedalus_ctx *ctx,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta)
+{
+    if (!ctx->h264deblock_h_pipe_ready) {
+        if (v3d_runner_create_pipeline(ctx->runner, "v3d_h264deblock_h.spv",
+                                       2, sizeof(h264deblock_pc), &ctx->h264deblock_h_pipe) != 0)
+            return -1;
+        ctx->h264deblock_h_pipe_ready = 1;
+    }
+
+    size_t meta_bytes = n_edges * 4 * sizeof(uint32_t);
+    /* H variant: reads cols [-4..+3] of 16 ROWS.  Each lane processes one row.
+     * Max addressed byte = dst_off + 15*stride + 3 (last row, col +3). */
+    size_t dst_max = 0;
+    for (size_t i = 0; i < n_edges; i++) {
+        size_t e = meta[i].dst_off + 15 * dst_stride + 4;
+        if (e > dst_max) dst_max = e;
+    }
+
+    v3d_buffer bm = {0}, bd = {0};
+    if (v3d_runner_acquire_buffer(ctx->runner, meta_bytes, &bm)) return -1;
+    if (v3d_runner_acquire_buffer(ctx->runner, dst_max,    &bd)) { v3d_runner_release_buffer(ctx->runner, &bm); return -1; }
+
+    memcpy(bd.mapped, dst, dst_max);
+    uint32_t *m = bm.mapped;
+    for (size_t i = 0; i < n_edges; i++) {
+        m[4*i+0] = meta[i].dst_off;
+        m[4*i+1] = ((uint32_t) meta[i].alpha) | (((uint32_t) meta[i].beta) << 8);
+        m[4*i+2] = ((uint32_t)(uint8_t) meta[i].tc0[0])
+                 | (((uint32_t)(uint8_t) meta[i].tc0[1]) << 8)
+                 | (((uint32_t)(uint8_t) meta[i].tc0[2]) << 16)
+                 | (((uint32_t)(uint8_t) meta[i].tc0[3]) << 24);
+        m[4*i+3] = 0;
+    }
+
+    v3d_buffer binds[2] = { bm, bd };
+    if (v3d_runner_bind_buffers(ctx->runner, &ctx->h264deblock_h_pipe, binds, 2)) goto fail;
+
+    uint32_t wg_count = (uint32_t)((n_edges + 15) / 16);
+    h264deblock_pc pc = { .n_edges = (uint32_t) n_edges,
+                          .dst_stride_u8 = (uint32_t) dst_stride };
+    if (v3d_runner_pipeline_cmdbuf_reset(ctx->runner, &ctx->h264deblock_h_pipe)) goto fail;
+    VkCommandBuffer cb = ctx->h264deblock_h_pipe.cb;
+    VkCommandBufferBeginInfo cbbi = { .sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_BEGIN_INFO };
+    vkBeginCommandBuffer(cb, &cbbi);
+    vkCmdBindPipeline(cb, VK_PIPELINE_BIND_POINT_COMPUTE, ctx->h264deblock_h_pipe.pipeline);
+    vkCmdBindDescriptorSets(cb, VK_PIPELINE_BIND_POINT_COMPUTE,
+                            ctx->h264deblock_h_pipe.layout, 0, 1, &ctx->h264deblock_h_pipe.desc_set, 0, NULL);
+    vkCmdPushConstants(cb, ctx->h264deblock_h_pipe.layout, VK_SHADER_STAGE_COMPUTE_BIT,
+                       0, sizeof(pc), &pc);
+    vkCmdDispatch(cb, wg_count, 1, 1);
+    vkEndCommandBuffer(cb);
+    if (v3d_runner_submit_wait(ctx->runner, cb)) goto fail;
+
+    memcpy(dst, bd.mapped, dst_max);
+
+    v3d_runner_release_buffer(ctx->runner, &bd);
+    v3d_runner_release_buffer(ctx->runner, &bm);
+    return 0;
+fail:
+    v3d_runner_release_buffer(ctx->runner, &bd);
+    v3d_runner_release_buffer(ctx->runner, &bm);
+    return -1;
+}
+
 /* -------------------- H.264 IDCT 4x4 QPU dispatch (cycle 6) ----- */
 
 typedef struct {
@@ -1433,20 +1504,11 @@ int daedalus_dispatch_h264_deblock_luma_h(daedalus_ctx *ctx, daedalus_substrate
     daedalus_substrate eff = sub;
     if (eff == DAEDALUS_SUBSTRATE_AUTO)
         eff = daedalus_recipe_substrate_for(DAEDALUS_KERNEL_H264_DEBLOCK_LH);
-    /* No QPU shader for the H variant yet — always falls through to
-     * CPU.  Mirror the _v shape anyway so the substrate switch is
-     * uniform; QPU just isn't a real option here yet. */
     if (eff == DAEDALUS_SUBSTRATE_QPU && !daedalus_ctx_has_qpu(ctx))
         eff = DAEDALUS_SUBSTRATE_CPU;
-    if (eff == DAEDALUS_SUBSTRATE_QPU) {
+    if (eff == DAEDALUS_SUBSTRATE_CPU)
-        /* QPU shader for H deblock isn't implemented yet; recipe
+        return dispatch_h264_deblock_h_cpu(ctx, dst, dst_stride, n_edges, meta);
-         * table returns CPU, so AUTO never lands here.  An explicit
+    return dispatch_h264_deblock_h_qpu(ctx, dst, dst_stride, n_edges, meta);
-         * QPU request fails fast rather than silently degrading to
-         * CPU — matches the principle from the IDCT QPU substrate
-         * (explicit means explicit). */
-        return -1;
-    }
-    return dispatch_h264_deblock_h_cpu(ctx, dst, dst_stride, n_edges, meta);
 }
 
 int daedalus_dispatch_h264_deblock_chroma_v(daedalus_ctx *ctx, daedalus_substrate sub,

src/v3d_h264deblock_h.comp

@@ -0,0 +1,111 @@
+// daedalus-fourier — H.264 luma "h_loop_filter" (horizontal filtering
+// across a vertical edge), non-intra bS<4 variant.  Sibling of cycle 8's
+// v3d_h264deblock.comp; same algorithm with row/col access transposed.
+//
+// V3D 7.1 via Mesa v3dv compute.  Same WG geometry as the V shader:
+//   - 256 invocations / WG, 16 edges/WG (16 lanes/edge = 1 sg/edge)
+//   - uint8_t dst SSBO via storageBuffer8BitAccess
+//   - No barrier (each lane independent)
+//   - lane_in_edge = ROW index (0..15) along the vertical edge
+//   - meta.dst_off points to (row 0, col 0) of the RIGHT block;
+//     the kernel reads cols [-4..+3] of each row and writes [-2..+1].
+//
+// Filter contract (per H.264 §8.7.2.4):
+//   1. (m.x % pc.dst_stride_u8) ≥ 4   (kernel reads p3 at pix[-4])
+//   2. pc.dst_stride_u8 = byte stride between rows
+//   3. tc0_s pre-stored as signed int8 in m.z packed 4 bytes (one per
+//      4-row segment along the 16-row edge)
+//
+// License: BSD-2-Clause.  Algorithm transcribed from
+// tests/h264_h_loop_filter_luma_ref.c which mirrors FFmpeg
+// ff_h264_h_loop_filter_luma_neon (LGPL-2.1+).
+
+#version 450
+#extension GL_EXT_shader_8bit_storage              : require
+#extension GL_EXT_shader_explicit_arithmetic_types : require
+
+layout(local_size_x = 256, local_size_y = 1, local_size_z = 1) in;
+
+layout(binding = 0) readonly buffer Meta {
+    uvec4 meta[];   // per edge: (dst_off, alpha|beta<<8, packed_tc0, _pad)
+} u_meta;
+
+layout(binding = 1) buffer Dst {
+    uint8_t dst[];
+} u_dst;
+
+layout(push_constant) uniform PC {
+    uint n_edges;
+    uint dst_stride_u8;
+    uint _pad0;
+    uint _pad1;
+} pc;
+
+void main()
+{
+    uint gid          = gl_GlobalInvocationID.x;
+    uint wg_id        = gl_WorkGroupID.x;
+    uint lane_in_wg   = gid & 255u;
+    uint edge_in_wg   = lane_in_wg >> 4;       // 0..15 (16 edges/WG)
+    uint row_in_edge  = lane_in_wg & 15u;      // 0..15 — ROW along the V edge
+
+    uint edge_idx = wg_id * 16u + edge_in_wg;
+    if (edge_idx >= pc.n_edges) return;
+
+    uvec4 m = u_meta.meta[edge_idx];
+    uint stride = pc.dst_stride_u8;
+    // dst_off addresses row 0 col 0 of the right block; advance by row * stride
+    // to land at this lane's row.  The kernel reads pix[-4..+3] AT THIS ROW.
+    uint dst_off = m.x + row_in_edge * stride;
+    int alpha = int(m.y & 0xffu);
+    int beta  = int((m.y >> 8) & 0xffu);
+
+    // tc0 segment = 0..3 indexed by (row_in_edge / 4).
+    uint seg = row_in_edge >> 2;
+    uint tc0_byte = (m.z >> (seg * 8u)) & 0xffu;
+    int tc0_s = int(tc0_byte);
+    if (tc0_s >= 128) tc0_s -= 256;
+
+    if (alpha == 0 || beta == 0) return;
+    if (tc0_s < 0) return;                     // segment skip
+
+    // Horizontal access pattern — read cols at offsets [-3..+2] of this row.
+    // p3 (col -4) unused in bS<4; same DCE comment as the V shader.
+    int p2 = int(u_dst.dst[dst_off - 3u]);
+    int p1 = int(u_dst.dst[dst_off - 2u]);
+    int p0 = int(u_dst.dst[dst_off - 1u]);
+    int q0 = int(u_dst.dst[dst_off       ]);
+    int q1 = int(u_dst.dst[dst_off + 1u]);
+    int q2 = int(u_dst.dst[dst_off + 2u]);
+
+    // Edge preconditions (same as V).
+    if (abs(p0 - q0) >= alpha) return;
+    if (abs(p1 - p0) >= beta)  return;
+    if (abs(q1 - q0) >= beta)  return;
+
+    int ap = abs(p2 - p0);
+    int aq = abs(q2 - q0);
+    bool ap_lt = ap < beta;
+    bool aq_lt = aq < beta;
+    int tc = tc0_s + int(ap_lt) + int(aq_lt);
+
+    int delta = clamp(((q0 - p0) * 4 + (p1 - q1) + 4) >> 3, -tc, tc);
+    int p0p = clamp(p0 + delta, 0, 255);
+    int q0p = clamp(q0 - delta, 0, 255);
+
+    int p1p = p1;
+    if (ap_lt) {
+        int d_p1 = clamp((p2 + ((p0 + q0 + 1) >> 1) - 2*p1) >> 1, -tc0_s, tc0_s);
+        p1p = clamp(p1 + d_p1, 0, 255);
+    }
+    int q1p = q1;
+    if (aq_lt) {
+        int d_q1 = clamp((q2 + ((p0 + q0 + 1) >> 1) - 2*q1) >> 1, -tc0_s, tc0_s);
+        q1p = clamp(q1 + d_q1, 0, 255);
+    }
+
+    u_dst.dst[dst_off - 2u] = uint8_t(p1p);
+    u_dst.dst[dst_off - 1u] = uint8_t(p0p);
+    u_dst.dst[dst_off       ] = uint8_t(q0p);
+    u_dst.dst[dst_off + 1u] = uint8_t(q1p);
+}