h264: deblock bS=4 intra variants (luma + chroma, V + H)

Closes the deblock matrix: adds the four bS=4 intra-strength loop
filters used at I-MB edges (and other boundaries where H.264
§8.7.2.1 forces boundary strength to 4).  After this PR fourier
covers all 8 standard 8-bit 4:2:0 deblock combinations:

    bS<4   bS=4
    -----  -----
  luma_v  ✓ (cycle 8 QPU)   ✓ (CPU)
  luma_h  ✓ (CPU, PR #9)    ✓ (CPU)
  chrm_v  ✓ (CPU, PR #10)   ✓ (CPU)
  chrm_h  ✓ (CPU, PR #10)   ✓ (CPU)

Scope:
  - 4 new kernel enums (LV_INTRA=13, LH_INTRA=14, CV_INTRA=15,
    CH_INTRA=16), all → CPU substrate in the recipe table.
  - 4 new public dispatch fns + 4 recipe wrappers (defined via two
    DEFINE_INTRA_DISPATCH / DEFINE_INTRA_RECIPE macros to keep the
    boilerplate tight).
  - 4 new extern decls for the vendored
    ff_h264_{v,h}_loop_filter_{luma,chroma}_intra_neon symbols.
  - C reference: tests/h264_intra_loop_filter_ref.c covers all four
    orientations.  Algorithm per H.264 §8.7.2.3:

      Luma: per-side strong/weak filter selector
        strong_p = (|p2-p0| < β) AND (|p0-q0| < (α>>2)+2)
        strong_q = (|q2-q0| < β) AND (|p0-q0| < (α>>2)+2)
        Strong updates p0/p1/p2 (and mirror); weak updates p0 only.
      Chroma: always weak, only p0/q0 updated.

  - daedalus_h264_deblock_meta is REUSED for intra dispatches; the
    tc0[] field is ignored (bS=4 hardcodes the strength).  Callers
    can build a single edge list and route by kernel without an
    extra struct.

  - Test refactor: an intra_test_spec table + run_intra_test helper
    drives all four orientations through one harness, keeping the
    new test surface compact (~50 LOC for 4 kernels vs ~200 if each
    had its own test_deblock_*_intra fn).

Verified on hertz (Pi 5 / V3D 7.1):

  $ ./build/test_api_h264
  === Phase 8a API smoke: H.264 kernels via recipe dispatch ===
    ...
    H.264 deblock luma v intra: 1024/1024 bytes bit-exact (100.0000%)
    H.264 deblock luma h intra: 1024/1024 bytes bit-exact (100.0000%)
    H.264 deblock chroma v intra: 256/256 bytes bit-exact (100.0000%)
    H.264 deblock chroma h intra: 256/256 bytes bit-exact (100.0000%)
    ...

  All 11 H.264 kernels bit-exact PASS — the deblock matrix is closed.

The bit-exact match on first try is meaningful for these kernels:
the strong/weak filter selector + per-side asymmetry would have
surfaced any sign / shift / rounding mistake immediately.  The
C reference is now a usable spec checkpoint for the eventual QPU
shader work.

QPU shader follow-up: not in this PR.  The intra path's 3-cell
per-side update + strong/weak branch is structurally more complex
than the bS<4 path that already has a V shader (v3d_h264deblock.spv).
Per the prior R-band logic for deblock, intra edges are < 20% of
total deblock work at typical bit-rates, so NEON-only at ~ 10 ns/edge
fits comfortably in the budget.

include/daedalus.h

@@ -315,6 +315,50 @@ int daedalus_dispatch_h264_deblock_chroma_h(daedalus_ctx *ctx, daedalus_substrat
     uint8_t *dst, size_t dst_stride,
     size_t n_edges, const daedalus_h264_deblock_meta *meta);
 
+/* H.264 bS=4 "intra" loop filters — used at I-MB and inter
+ * macroblock boundaries where boundary strength is forced to 4 per
+ * H.264 §8.7.2.1.  Different algorithm from bS<4: per-side strong
+ * vs weak filter decided by quad-tree condition (luma only);
+ * chroma is always weak.  No tc0 — the daedalus_h264_deblock_meta
+ * struct's tc0[] field is IGNORED for intra dispatches (callers can
+ * leave it uninitialised or share a single edge list across both
+ * intra and non-intra kernels).
+ *
+ * Reuses the same meta layout as bS<4 dispatches for alpha + beta +
+ * dst_off; tile geometry per orientation is identical to the bS<4
+ * sibling (16-col / 16-row luma; 8-col / 8-row chroma).
+ *
+ * QPU shaders not implemented for any of the four; recipe routes
+ * AUTO to CPU NEON.  Explicit SUBSTRATE_QPU returns -1 (fast fail).
+ */
+int daedalus_recipe_dispatch_h264_deblock_luma_v_intra(daedalus_ctx *ctx,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+int daedalus_dispatch_h264_deblock_luma_v_intra(daedalus_ctx *ctx, daedalus_substrate sub,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+
+int daedalus_recipe_dispatch_h264_deblock_luma_h_intra(daedalus_ctx *ctx,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+int daedalus_dispatch_h264_deblock_luma_h_intra(daedalus_ctx *ctx, daedalus_substrate sub,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+
+int daedalus_recipe_dispatch_h264_deblock_chroma_v_intra(daedalus_ctx *ctx,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+int daedalus_dispatch_h264_deblock_chroma_v_intra(daedalus_ctx *ctx, daedalus_substrate sub,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+
+int daedalus_recipe_dispatch_h264_deblock_chroma_h_intra(daedalus_ctx *ctx,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+int daedalus_dispatch_h264_deblock_chroma_h_intra(daedalus_ctx *ctx, daedalus_substrate sub,
+    uint8_t *dst, size_t dst_stride,
+    size_t n_edges, const daedalus_h264_deblock_meta *meta);
+
 /* -------------------------------------------------------------------
  * H.264 luma qpel mc20 (8×8, horizontal half-pel) — cycle 9
  * (CPU by recipe; per-block 7.6 ns NEON, QPU not viable — see
@@ -364,6 +408,10 @@ typedef enum {
     DAEDALUS_KERNEL_H264_DEBLOCK_LH = 10,
     DAEDALUS_KERNEL_H264_DEBLOCK_CV = 11,
     DAEDALUS_KERNEL_H264_DEBLOCK_CH = 12,
+    DAEDALUS_KERNEL_H264_DEBLOCK_LV_INTRA = 13,
+    DAEDALUS_KERNEL_H264_DEBLOCK_LH_INTRA = 14,
+    DAEDALUS_KERNEL_H264_DEBLOCK_CV_INTRA = 15,
+    DAEDALUS_KERNEL_H264_DEBLOCK_CH_INTRA = 16,
 } daedalus_kernel;
 
 daedalus_substrate daedalus_recipe_substrate_for(daedalus_kernel k);