h264: V3D shader for qpel mc02 (vertical half-pel)
Sibling of cycle 9's v3d_h264_qpel_mc20.comp. Same 6-tap H.264 luma
half-pel filter, transposed to vertical orientation: filter reads
rows [-2..+3] of source per output pixel instead of cols.
Shader is ~58 lines (vs mc20's 86) — same WG geometry (64 lanes /
1 block per WG / 1 lane per output pixel). The address arithmetic
flips: row_base = src_off + r*stride + c (mc20) → col_base =
src_off + c, then col_base + (r±N)*stride (mc02).
dispatch_h264_qpel_mc02_qpu mirrors the mc20 QPU dispatch; src_max
calculation differs since the V kernel reads rows -2..+10 of source
(13 rows × stride wide) vs mc20's cols -2..+10 (8 rows × stride+11).
For 8x8 blocks: src_max = src_off + 10*stride + 8.
Recipe table flips DAEDALUS_KERNEL_H264_QPEL_MC02 from CPU to QPU.
Verified on hertz:
$ ./build/test_api_h264 | grep qpel
H.264 qpel mc20: 1024/1024 bytes bit-exact (100.0000%)
H.264 qpel mc02: 2048/2048 bytes bit-exact (100.0000%)
QPU coverage for the 30 qpel positions:
put_ mc20 ✓ (cycle 9) mc02 ✓ (this PR)
all 13 other put_ CPU NEON
avg_ all 15 positions CPU NEON
Next-priority candidates by per-frame impact (per PR #24 bench):
mc22 (2D half-pel) — 71.5 ns/block NEON × 32 640 blocks worst
case = 2.33 ms/frame at 1080p. Most-used
qpel position in real H.264 streams.
mc11/mc13/mc31/mc33 — corner ¼-pel positions, structurally similar
to mc20 + mc02 with L2 averaging.
The cascaded H+V structure of mc22 means it can either share the
existing mc20 + mc02 shaders' L2 (compute mc20 into tmp, then mc02
on tmp) or get a dedicated 2-stage pipeline. Follow-up.
This commit is contained in:
+90
-4
@@ -52,6 +52,8 @@ struct daedalus_ctx {
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v3d_pipeline h264_idct8_pipe;
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int h264_qpel_mc20_pipe_ready;
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v3d_pipeline h264_qpel_mc20_pipe;
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int h264_qpel_mc02_pipe_ready;
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v3d_pipeline h264_qpel_mc02_pipe;
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};
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daedalus_ctx *daedalus_ctx_create(void)
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@@ -112,6 +114,7 @@ void daedalus_ctx_destroy(daedalus_ctx *ctx)
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if (ctx->h264_idct4_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_idct4_pipe);
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if (ctx->h264_idct8_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_idct8_pipe);
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if (ctx->h264_qpel_mc20_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_qpel_mc20_pipe);
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if (ctx->h264_qpel_mc02_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_qpel_mc02_pipe);
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v3d_runner_destroy(ctx->runner);
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}
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free(ctx);
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@@ -147,7 +150,7 @@ daedalus_substrate daedalus_recipe_substrate_for(daedalus_kernel k)
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case DAEDALUS_KERNEL_H264_DEBLOCK_CV_INTRA: return DAEDALUS_SUBSTRATE_CPU; /* bS=4 chroma QPU pending */
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case DAEDALUS_KERNEL_H264_DEBLOCK_CH_INTRA: return DAEDALUS_SUBSTRATE_CPU;
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case DAEDALUS_KERNEL_H264_QPEL_MC20: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264_qpel_mc20.spv */
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case DAEDALUS_KERNEL_H264_QPEL_MC02: return DAEDALUS_SUBSTRATE_CPU; /* QPU mc02 shader pending */
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case DAEDALUS_KERNEL_H264_QPEL_MC02: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264_qpel_mc02.spv */
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case DAEDALUS_KERNEL_H264_QPEL_MC22: return DAEDALUS_SUBSTRATE_CPU; /* QPU mc22 shader pending (hv lowpass) */
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case DAEDALUS_KERNEL_H264_QPEL_MC10: return DAEDALUS_SUBSTRATE_CPU; /* ¼-H L2 */
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case DAEDALUS_KERNEL_H264_QPEL_MC30: return DAEDALUS_SUBSTRATE_CPU; /* ¾-H L2 */
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@@ -1457,6 +1460,89 @@ fail:
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return -1;
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}
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static int dispatch_h264_qpel_mc02_qpu(daedalus_ctx *ctx,
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uint8_t *dst, const uint8_t *src, size_t stride,
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size_t n_blocks, const daedalus_h264_qpel_meta *meta)
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{
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/* Same shape as mc20 but with vertical access pattern. src_max
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* reflects the row-wise filter window: bottom output row (r=7)
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* reads up to row r+3 = 10 of the src; so src_max = src_off +
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* 10*stride + 8 (last col + 1 for memcpy semantics). */
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if (!ctx->h264_qpel_mc02_pipe_ready) {
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if (v3d_runner_create_pipeline(ctx->runner, "v3d_h264_qpel_mc02.spv",
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3, sizeof(h264_qpel_mc20_pc),
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&ctx->h264_qpel_mc02_pipe) != 0)
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return -1;
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ctx->h264_qpel_mc02_pipe_ready = 1;
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}
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size_t meta_bytes = n_blocks * 4 * sizeof(uint32_t);
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size_t src_max = 0, dst_max = 0;
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for (size_t i = 0; i < n_blocks; i++) {
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size_t s_end = meta[i].src_off + (size_t) 10 * stride + 8;
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size_t d_end = meta[i].dst_off + (size_t) 7 * stride + 8;
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if (s_end > src_max) src_max = s_end;
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if (d_end > dst_max) dst_max = d_end;
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}
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v3d_buffer bs = {0}, bd = {0}, bm = {0};
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if (v3d_runner_create_buffer(ctx->runner, src_max, &bs)) return -1;
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if (v3d_runner_create_buffer(ctx->runner, dst_max, &bd)) {
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v3d_runner_destroy_buffer(ctx->runner, &bs); return -1;
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}
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if (v3d_runner_create_buffer(ctx->runner, meta_bytes, &bm)) {
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v3d_runner_destroy_buffer(ctx->runner, &bd);
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v3d_runner_destroy_buffer(ctx->runner, &bs); return -1;
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}
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memcpy(bs.mapped, src, src_max);
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memcpy(bd.mapped, dst, dst_max);
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uint32_t *m = bm.mapped;
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for (size_t i = 0; i < n_blocks; i++) {
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m[4*i+0] = meta[i].dst_off;
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m[4*i+1] = meta[i].src_off;
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m[4*i+2] = 0;
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m[4*i+3] = 0;
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}
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v3d_buffer binds[3] = { bs, bd, bm };
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if (v3d_runner_bind_buffers(ctx->runner, &ctx->h264_qpel_mc02_pipe, binds, 3))
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goto fail;
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uint32_t wg_count = (uint32_t) n_blocks;
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h264_qpel_mc20_pc pc = {
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.n_blocks = (uint32_t) n_blocks,
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.stride_u8 = (uint32_t) stride,
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};
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VkCommandBuffer cb = v3d_runner_alloc_cmdbuf(ctx->runner);
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if (cb == VK_NULL_HANDLE) goto fail;
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VkCommandBufferBeginInfo cbbi = { .sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_BEGIN_INFO };
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vkBeginCommandBuffer(cb, &cbbi);
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vkCmdBindPipeline(cb, VK_PIPELINE_BIND_POINT_COMPUTE,
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ctx->h264_qpel_mc02_pipe.pipeline);
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vkCmdBindDescriptorSets(cb, VK_PIPELINE_BIND_POINT_COMPUTE,
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ctx->h264_qpel_mc02_pipe.layout, 0, 1,
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&ctx->h264_qpel_mc02_pipe.desc_set, 0, NULL);
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vkCmdPushConstants(cb, ctx->h264_qpel_mc02_pipe.layout,
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VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(pc), &pc);
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vkCmdDispatch(cb, wg_count, 1, 1);
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vkEndCommandBuffer(cb);
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if (v3d_runner_submit_wait(ctx->runner, cb)) goto fail;
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memcpy(dst, bd.mapped, dst_max);
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v3d_runner_destroy_buffer(ctx->runner, &bm);
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v3d_runner_destroy_buffer(ctx->runner, &bd);
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v3d_runner_destroy_buffer(ctx->runner, &bs);
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return 0;
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fail:
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v3d_runner_destroy_buffer(ctx->runner, &bm);
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v3d_runner_destroy_buffer(ctx->runner, &bd);
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v3d_runner_destroy_buffer(ctx->runner, &bs);
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return -1;
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}
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/* -------------------- Public dispatch entry points -------------- */
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#define ROUTE_CPU_ONLY(_kernel, _cpu_fn, ...) \
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@@ -1676,9 +1762,9 @@ int daedalus_dispatch_h264_qpel_mc02(daedalus_ctx *ctx, daedalus_substrate sub,
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eff = daedalus_recipe_substrate_for(DAEDALUS_KERNEL_H264_QPEL_MC02);
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if (eff == DAEDALUS_SUBSTRATE_QPU && !daedalus_ctx_has_qpu(ctx))
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eff = DAEDALUS_SUBSTRATE_CPU;
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if (eff == DAEDALUS_SUBSTRATE_QPU)
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return -1; /* No mc02 QPU shader yet — explicit QPU fast-fails. */
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return dispatch_h264_qpel_mc02_cpu(ctx, dst, src, stride, n_blocks, meta);
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if (eff == DAEDALUS_SUBSTRATE_CPU)
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return dispatch_h264_qpel_mc02_cpu(ctx, dst, src, stride, n_blocks, meta);
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return dispatch_h264_qpel_mc02_qpu(ctx, dst, src, stride, n_blocks, meta);
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}
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int daedalus_dispatch_h264_qpel_mc22(daedalus_ctx *ctx, daedalus_substrate sub,
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