h264: V3D shaders for chroma deblock V + H (4:2:0)
Adds the QPU shader pair for chroma_v / chroma_h deblock (non-intra bS<4), siblings of the cycle 8 luma_v shader and PR #28's luma_h. Closes 4 of 8 deblock QPU coverage at non-intra: luma_v ✓ cycle 8 luma_h ✓ PR #28 chroma_v ✓ this PR chroma_h ✓ this PR *_intra — CPU NEON (less common; smaller volume) Per H.264 §8.7.2.4 chroma kernel is simpler than luma: only p0/q0 updated (never p1/p2/q1/q2), tC = tc0_seg + 1 (no luma-style ap/aq side bonus), 8 cells per edge (vs luma's 16). Shader: 64 lines vs luma_v's 108 — same WG geometry (16 edges × 16 lanes, lanes 8..15 of each edge early-return). 4:2:0-only: 4:2:2 chroma_h has a 16-row edge geometry that this shader doesn't address; daedalus_dispatch_h264_deblock_chroma_h is 4:2:0-only by design, caller-side gating already covers this in the libavcodec substitution arc (marfrit-packages PR #98). Recipe table flips DAEDALUS_KERNEL_H264_DEBLOCK_CV / CH from CPU to QPU. dispatch_h264_deblock_chroma_qpu factored to share QPU plumbing between V and H (orientation passed as a flag for the dst_max calculation). Verified on hertz: $ ./build/test_api_h264 | grep "deblock chroma [vh]:" H.264 deblock chroma v: 256/256 bytes bit-exact (100.0000%) H.264 deblock chroma h: 256/256 bytes bit-exact (100.0000%) Recipe substrate now reports 2 (QPU) for both CV and CH. Coverage now: bS<4 QPU bS=4 (intra) luma_v ✓ cycle 8 CPU NEON luma_h ✓ PR #28 CPU NEON chroma_v ✓ this PR CPU NEON chroma_h ✓ this PR CPU NEON Intra (bS=4) variants stay CPU NEON. Less common case, smaller per-frame contribution, and the algorithm is structurally different (no tc0; strong-vs-weak filter quad-tree). Can land as a follow-up PR if perf demands.
This commit is contained in:
+99
-8
@@ -42,6 +42,10 @@ struct daedalus_ctx {
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v3d_pipeline h264deblock_pipe;
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int h264deblock_h_pipe_ready;
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v3d_pipeline h264deblock_h_pipe;
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int h264deblock_chroma_v_pipe_ready;
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v3d_pipeline h264deblock_chroma_v_pipe;
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int h264deblock_chroma_h_pipe_ready;
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v3d_pipeline h264deblock_chroma_h_pipe;
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int h264_idct4_pipe_ready;
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v3d_pipeline h264_idct4_pipe;
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int h264_idct8_pipe_ready;
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@@ -103,6 +107,8 @@ void daedalus_ctx_destroy(daedalus_ctx *ctx)
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if (ctx->cdef_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->cdef_pipe);
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if (ctx->h264deblock_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264deblock_pipe);
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if (ctx->h264deblock_h_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264deblock_h_pipe);
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if (ctx->h264deblock_chroma_v_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264deblock_chroma_v_pipe);
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if (ctx->h264deblock_chroma_h_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264deblock_chroma_h_pipe);
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if (ctx->h264_idct4_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_idct4_pipe);
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if (ctx->h264_idct8_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_idct8_pipe);
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if (ctx->h264_qpel_mc20_pipe_ready) v3d_runner_destroy_pipeline(ctx->runner, &ctx->h264_qpel_mc20_pipe);
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@@ -134,8 +140,8 @@ daedalus_substrate daedalus_recipe_substrate_for(daedalus_kernel k)
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case DAEDALUS_KERNEL_H264_IDCT8: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264_idct8.spv */
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case DAEDALUS_KERNEL_H264_DEBLOCK_LV: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264deblock.spv */
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case DAEDALUS_KERNEL_H264_DEBLOCK_LH: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264deblock_h.spv */
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case DAEDALUS_KERNEL_H264_DEBLOCK_CV: return DAEDALUS_SUBSTRATE_CPU; /* chroma QPU pending */
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case DAEDALUS_KERNEL_H264_DEBLOCK_CH: return DAEDALUS_SUBSTRATE_CPU; /* chroma QPU pending */
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case DAEDALUS_KERNEL_H264_DEBLOCK_CV: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264deblock_chroma_v.spv */
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case DAEDALUS_KERNEL_H264_DEBLOCK_CH: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264deblock_chroma_h.spv */
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case DAEDALUS_KERNEL_H264_DEBLOCK_LV_INTRA: return DAEDALUS_SUBSTRATE_CPU; /* bS=4 luma QPU pending */
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case DAEDALUS_KERNEL_H264_DEBLOCK_LH_INTRA: return DAEDALUS_SUBSTRATE_CPU;
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case DAEDALUS_KERNEL_H264_DEBLOCK_CV_INTRA: return DAEDALUS_SUBSTRATE_CPU; /* bS=4 chroma QPU pending */
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@@ -1084,6 +1090,91 @@ fail:
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return -1;
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}
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/* -------------------- H.264 chroma deblock QPU dispatch -------- */
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/* Generic chroma QPU dispatch (shared between V and H variants).
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* Both shaders use 8 cells per edge; max-addressed-byte differs:
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* V: dst_off + 1*stride + 7 (-2..+1 rows, cols 0..7 of edge)
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* H: dst_off + 7*stride + 1 (-2..+1 cols, rows 0..7 of edge)
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* Caller passes the precomputed extent.
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*/
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static int dispatch_h264_deblock_chroma_qpu(daedalus_ctx *ctx,
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v3d_pipeline *pipe, int *pipe_ready, const char *spv_name,
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uint8_t *dst, size_t dst_stride, size_t n_edges,
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const daedalus_h264_deblock_meta *meta, int orient_h)
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{
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if (!*pipe_ready) {
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if (v3d_runner_create_pipeline(ctx->runner, spv_name,
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2, sizeof(h264deblock_pc), pipe) != 0)
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return -1;
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*pipe_ready = 1;
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}
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size_t meta_bytes = n_edges * 4 * sizeof(uint32_t);
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size_t dst_max = 0;
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for (size_t i = 0; i < n_edges; i++) {
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size_t e = orient_h ? meta[i].dst_off + 7 * dst_stride + 2
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: meta[i].dst_off + 1 * dst_stride + 8;
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if (e > dst_max) dst_max = e;
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}
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v3d_buffer bm = {0}, bd = {0};
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if (v3d_runner_acquire_buffer(ctx->runner, meta_bytes, &bm)) return -1;
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if (v3d_runner_acquire_buffer(ctx->runner, dst_max, &bd)) { v3d_runner_release_buffer(ctx->runner, &bm); return -1; }
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memcpy(bd.mapped, dst, dst_max);
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uint32_t *m = bm.mapped;
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for (size_t i = 0; i < n_edges; i++) {
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m[4*i+0] = meta[i].dst_off;
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m[4*i+1] = ((uint32_t) meta[i].alpha) | (((uint32_t) meta[i].beta) << 8);
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m[4*i+2] = ((uint32_t)(uint8_t) meta[i].tc0[0])
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| (((uint32_t)(uint8_t) meta[i].tc0[1]) << 8)
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| (((uint32_t)(uint8_t) meta[i].tc0[2]) << 16)
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| (((uint32_t)(uint8_t) meta[i].tc0[3]) << 24);
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m[4*i+3] = 0;
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}
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v3d_buffer binds[2] = { bm, bd };
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if (v3d_runner_bind_buffers(ctx->runner, pipe, binds, 2)) goto fail;
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uint32_t wg_count = (uint32_t)((n_edges + 15) / 16);
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h264deblock_pc pc = { .n_edges = (uint32_t) n_edges,
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.dst_stride_u8 = (uint32_t) dst_stride };
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if (v3d_runner_pipeline_cmdbuf_reset(ctx->runner, pipe)) goto fail;
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VkCommandBuffer cb = pipe->cb;
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VkCommandBufferBeginInfo cbbi = { .sType = VK_STRUCTURE_TYPE_COMMAND_BUFFER_BEGIN_INFO };
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vkBeginCommandBuffer(cb, &cbbi);
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vkCmdBindPipeline(cb, VK_PIPELINE_BIND_POINT_COMPUTE, pipe->pipeline);
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vkCmdBindDescriptorSets(cb, VK_PIPELINE_BIND_POINT_COMPUTE,
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pipe->layout, 0, 1, &pipe->desc_set, 0, NULL);
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vkCmdPushConstants(cb, pipe->layout, VK_SHADER_STAGE_COMPUTE_BIT,
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0, sizeof(pc), &pc);
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vkCmdDispatch(cb, wg_count, 1, 1);
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vkEndCommandBuffer(cb);
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if (v3d_runner_submit_wait(ctx->runner, cb)) goto fail;
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memcpy(dst, bd.mapped, dst_max);
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v3d_runner_release_buffer(ctx->runner, &bd);
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v3d_runner_release_buffer(ctx->runner, &bm);
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return 0;
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fail:
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v3d_runner_release_buffer(ctx->runner, &bd);
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v3d_runner_release_buffer(ctx->runner, &bm);
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return -1;
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}
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static int dispatch_h264_deblock_chroma_v_qpu(daedalus_ctx *ctx,
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uint8_t *dst, size_t dst_stride,
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size_t n_edges, const daedalus_h264_deblock_meta *meta)
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{
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return dispatch_h264_deblock_chroma_qpu(ctx,
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&ctx->h264deblock_chroma_v_pipe, &ctx->h264deblock_chroma_v_pipe_ready,
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"v3d_h264deblock_chroma_v.spv", dst, dst_stride, n_edges, meta, 0);
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}
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static int dispatch_h264_deblock_chroma_h_qpu(daedalus_ctx *ctx,
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uint8_t *dst, size_t dst_stride,
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size_t n_edges, const daedalus_h264_deblock_meta *meta)
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{
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return dispatch_h264_deblock_chroma_qpu(ctx,
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&ctx->h264deblock_chroma_h_pipe, &ctx->h264deblock_chroma_h_pipe_ready,
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"v3d_h264deblock_chroma_h.spv", dst, dst_stride, n_edges, meta, 1);
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}
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/* -------------------- H.264 IDCT 4x4 QPU dispatch (cycle 6) ----- */
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typedef struct {
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@@ -1520,9 +1611,9 @@ int daedalus_dispatch_h264_deblock_chroma_v(daedalus_ctx *ctx, daedalus_substrat
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eff = daedalus_recipe_substrate_for(DAEDALUS_KERNEL_H264_DEBLOCK_CV);
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if (eff == DAEDALUS_SUBSTRATE_QPU && !daedalus_ctx_has_qpu(ctx))
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eff = DAEDALUS_SUBSTRATE_CPU;
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if (eff == DAEDALUS_SUBSTRATE_QPU)
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return -1; /* No chroma QPU shader yet. */
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return dispatch_h264_deblock_chroma_v_cpu(ctx, dst, dst_stride, n_edges, meta);
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if (eff == DAEDALUS_SUBSTRATE_CPU)
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return dispatch_h264_deblock_chroma_v_cpu(ctx, dst, dst_stride, n_edges, meta);
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return dispatch_h264_deblock_chroma_v_qpu(ctx, dst, dst_stride, n_edges, meta);
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}
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int daedalus_dispatch_h264_deblock_chroma_h(daedalus_ctx *ctx, daedalus_substrate sub,
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@@ -1534,9 +1625,9 @@ int daedalus_dispatch_h264_deblock_chroma_h(daedalus_ctx *ctx, daedalus_substrat
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eff = daedalus_recipe_substrate_for(DAEDALUS_KERNEL_H264_DEBLOCK_CH);
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if (eff == DAEDALUS_SUBSTRATE_QPU && !daedalus_ctx_has_qpu(ctx))
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eff = DAEDALUS_SUBSTRATE_CPU;
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if (eff == DAEDALUS_SUBSTRATE_QPU)
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return -1;
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return dispatch_h264_deblock_chroma_h_cpu(ctx, dst, dst_stride, n_edges, meta);
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if (eff == DAEDALUS_SUBSTRATE_CPU)
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return dispatch_h264_deblock_chroma_h_cpu(ctx, dst, dst_stride, n_edges, meta);
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return dispatch_h264_deblock_chroma_h_qpu(ctx, dst, dst_stride, n_edges, meta);
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}
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#define DEFINE_INTRA_DISPATCH(name, kernel, cpu_fn) \
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