h264: qpel single-axis quarter-pel — mc10/mc30/mc01/mc03 (CPU/NEON)
Closes the 4 single-axis quarter-pel positions in one PR. Each is
a half-pel lowpass clipped to u8 followed by L2 rounded-average
with an integer-aligned source pixel per H.264 §8.4.2.2.1:
mc10 ¼-H ("a" pos): clip255(mc20(s)) avg src[r,c]
mc30 ¾-H ("c" pos): clip255(mc20(s)) avg src[r,c+1]
mc01 ¼-V ("d" pos): clip255(mc02(s)) avg src[r,c]
mc03 ¾-V ("n" pos): clip255(mc02(s)) avg src[r+1,c]
The mc10/mc30 pair and mc01/mc03 pair only differ in WHICH integer
source pixel they average with — the half-pel computation is the
same. Putting them in one PR is justified by that uniformity.
Scope:
- 4 new kernel enums: MC10=19, MC30=20, MC01=21, MC03=22 → CPU.
- 4 NEON externs for the vendored ff_put_h264_qpel8_mc{10,30,01,03}_neon.
- 4 CPU dispatch wrappers via DEFINE_QPEL_CPU_DISPATCH macro
(collapses ~50 LOC of repetition).
- 4 public dispatch fns via DEFINE_QPEL_DISPATCH macro.
- 4 recipe wrappers via DEFINE_QPEL_RECIPE macro.
- tests/h264_qpel8_quarter_axis_ref.c covers all four via shared
hpel_h() / hpel_v() inlines + per-mode L2 average.
- Test refactor: generic run_quarter_axis_qpel() harness exercises
all 4 positions through a single helper (~50 LOC for 4 tests vs
~200 if each was hand-rolled).
Verified on hertz:
$ ./build/test_api_h264 | tail -8
H.264 deblock chroma h intra: 256/256 bytes bit-exact (100.0000%)
H.264 qpel mc20: 1024/1024 bytes bit-exact (100.0000%)
H.264 qpel mc02: 2048/2048 bytes bit-exact (100.0000%)
H.264 qpel mc22: 2048/2048 bytes bit-exact (100.0000%)
H.264 qpel mc10: 2048/2048 bytes bit-exact (100.0000%)
H.264 qpel mc30: 2048/2048 bytes bit-exact (100.0000%)
H.264 qpel mc01: 2048/2048 bytes bit-exact (100.0000%)
H.264 qpel mc03: 2048/2048 bytes bit-exact (100.0000%)
All 4 new positions bit-exact PASS first try.
Coverage matrix update:
put_ mc00 mc10 mc20 mc30
mc01 — ✓ — ✓
mc11 — — ✓ — ← this row
mc21 — — — —
mc31 — — — —
mc02 — — ✓ — ← mc02 + mc22 anchor
mc03 — — ✓ —
After this PR: 7 of 16 single-axis + diagonal positions done.
Remaining 9 are the off-axis quarter-pel combinations
(mc11/mc12/mc13/mc21/mc23/mc31/mc32/mc33) — each combines a 2D
lowpass intermediate with L2 averaging against a 1D-lowpass output.
Next PR scope.
Why no QPU shaders: same R-band logic as the prior CPU additions.
At ~10 ns per 8x8 NEON block, all 16 qpel positions together
would land in ~1.3 ms/frame at 1080p worst case — comfortably
inside the 33 ms budget. QPU shader for mc20 already exists
(cycle 9 / v3d_h264_qpel_mc20.spv); the other 15 follow once a
clear perf reason emerges.
This commit is contained in:
@@ -140,6 +140,10 @@ daedalus_substrate daedalus_recipe_substrate_for(daedalus_kernel k)
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case DAEDALUS_KERNEL_H264_QPEL_MC20: return DAEDALUS_SUBSTRATE_QPU; /* v3d_h264_qpel_mc20.spv */
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case DAEDALUS_KERNEL_H264_QPEL_MC02: return DAEDALUS_SUBSTRATE_CPU; /* QPU mc02 shader pending */
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case DAEDALUS_KERNEL_H264_QPEL_MC22: return DAEDALUS_SUBSTRATE_CPU; /* QPU mc22 shader pending (hv lowpass) */
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case DAEDALUS_KERNEL_H264_QPEL_MC10: return DAEDALUS_SUBSTRATE_CPU; /* ¼-H L2 */
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case DAEDALUS_KERNEL_H264_QPEL_MC30: return DAEDALUS_SUBSTRATE_CPU; /* ¾-H L2 */
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case DAEDALUS_KERNEL_H264_QPEL_MC01: return DAEDALUS_SUBSTRATE_CPU; /* ¼-V L2 */
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case DAEDALUS_KERNEL_H264_QPEL_MC03: return DAEDALUS_SUBSTRATE_CPU; /* ¾-V L2 */
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}
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return DAEDALUS_SUBSTRATE_CPU;
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}
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@@ -184,6 +188,14 @@ extern void ff_put_h264_qpel8_mc02_neon(uint8_t *dst, const uint8_t *src,
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ptrdiff_t stride);
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extern void ff_put_h264_qpel8_mc22_neon(uint8_t *dst, const uint8_t *src,
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ptrdiff_t stride);
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extern void ff_put_h264_qpel8_mc10_neon(uint8_t *dst, const uint8_t *src,
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ptrdiff_t stride);
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extern void ff_put_h264_qpel8_mc30_neon(uint8_t *dst, const uint8_t *src,
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ptrdiff_t stride);
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extern void ff_put_h264_qpel8_mc01_neon(uint8_t *dst, const uint8_t *src,
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ptrdiff_t stride);
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extern void ff_put_h264_qpel8_mc03_neon(uint8_t *dst, const uint8_t *src,
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ptrdiff_t stride);
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/* -------------------- CPU dispatch implementations -------------- */
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@@ -437,6 +449,28 @@ static int dispatch_h264_qpel_mc22_cpu(daedalus_ctx *ctx,
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return 0;
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}
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/* The four single-axis quarter-pel CPU dispatches are uniform; the
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* macro collapses ~50 LOC of repetition. */
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#define DEFINE_QPEL_CPU_DISPATCH(suffix, neon_fn) \
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static int dispatch_h264_qpel_ ## suffix ## _cpu(daedalus_ctx *ctx, \
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uint8_t *dst, const uint8_t *src, size_t stride, \
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size_t n_blocks, const daedalus_h264_qpel_meta *meta) \
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{ \
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(void) ctx; \
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for (size_t i = 0; i < n_blocks; i++) { \
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neon_fn(dst + meta[i].dst_off, src + meta[i].src_off, \
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(ptrdiff_t) stride); \
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} \
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return 0; \
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}
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DEFINE_QPEL_CPU_DISPATCH(mc10, ff_put_h264_qpel8_mc10_neon)
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DEFINE_QPEL_CPU_DISPATCH(mc30, ff_put_h264_qpel8_mc30_neon)
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DEFINE_QPEL_CPU_DISPATCH(mc01, ff_put_h264_qpel8_mc01_neon)
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DEFINE_QPEL_CPU_DISPATCH(mc03, ff_put_h264_qpel8_mc03_neon)
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#undef DEFINE_QPEL_CPU_DISPATCH
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/* -------------------- IDCT QPU dispatch (cycle 1 v4 shader) ---- */
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typedef struct {
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@@ -1436,6 +1470,28 @@ int daedalus_dispatch_h264_qpel_mc22(daedalus_ctx *ctx, daedalus_substrate sub,
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return dispatch_h264_qpel_mc22_cpu(ctx, dst, src, stride, n_blocks, meta);
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}
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#define DEFINE_QPEL_DISPATCH(suffix, kernel) \
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int daedalus_dispatch_h264_qpel_ ## suffix(daedalus_ctx *ctx, \
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daedalus_substrate sub, uint8_t *dst, const uint8_t *src, size_t stride, \
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size_t n_blocks, const daedalus_h264_qpel_meta *meta) \
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{ \
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daedalus_substrate eff = sub; \
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if (eff == DAEDALUS_SUBSTRATE_AUTO) \
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eff = daedalus_recipe_substrate_for(kernel); \
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if (eff == DAEDALUS_SUBSTRATE_QPU && !daedalus_ctx_has_qpu(ctx)) \
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eff = DAEDALUS_SUBSTRATE_CPU; \
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if (eff == DAEDALUS_SUBSTRATE_QPU) return -1; \
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return dispatch_h264_qpel_ ## suffix ## _cpu(ctx, dst, src, stride, \
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n_blocks, meta); \
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}
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DEFINE_QPEL_DISPATCH(mc10, DAEDALUS_KERNEL_H264_QPEL_MC10)
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DEFINE_QPEL_DISPATCH(mc30, DAEDALUS_KERNEL_H264_QPEL_MC30)
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DEFINE_QPEL_DISPATCH(mc01, DAEDALUS_KERNEL_H264_QPEL_MC01)
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DEFINE_QPEL_DISPATCH(mc03, DAEDALUS_KERNEL_H264_QPEL_MC03)
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#undef DEFINE_QPEL_DISPATCH
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/* -------------------- Recipe convenience wrappers --------------- */
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int daedalus_recipe_dispatch_vp9_idct8(daedalus_ctx *ctx,
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@@ -1570,3 +1626,19 @@ int daedalus_recipe_dispatch_h264_qpel_mc22(daedalus_ctx *ctx,
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return daedalus_dispatch_h264_qpel_mc22(ctx, DAEDALUS_SUBSTRATE_AUTO,
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dst, src, stride, n_blocks, meta);
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}
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#define DEFINE_QPEL_RECIPE(suffix) \
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int daedalus_recipe_dispatch_h264_qpel_ ## suffix(daedalus_ctx *ctx, \
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uint8_t *dst, const uint8_t *src, size_t stride, \
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size_t n_blocks, const daedalus_h264_qpel_meta *meta) \
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{ \
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return daedalus_dispatch_h264_qpel_ ## suffix(ctx, DAEDALUS_SUBSTRATE_AUTO,\
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dst, src, stride, n_blocks, meta); \
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}
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DEFINE_QPEL_RECIPE(mc10)
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DEFINE_QPEL_RECIPE(mc30)
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DEFINE_QPEL_RECIPE(mc01)
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DEFINE_QPEL_RECIPE(mc03)
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#undef DEFINE_QPEL_RECIPE
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