// daedalus-fourier — H.264 luma "h_loop_filter" (horizontal filtering
// across a vertical edge), non-intra bS<4 variant.  Sibling of cycle 8's
// v3d_h264deblock.comp; same algorithm with row/col access transposed.
//
// V3D 7.1 via Mesa v3dv compute.  Same WG geometry as the V shader:
//   - 256 invocations / WG, 16 edges/WG (16 lanes/edge = 1 sg/edge)
//   - uint8_t dst SSBO via storageBuffer8BitAccess
//   - No barrier (each lane independent)
//   - lane_in_edge = ROW index (0..15) along the vertical edge
//   - meta.dst_off points to (row 0, col 0) of the RIGHT block;
//     the kernel reads cols [-4..+3] of each row and writes [-2..+1].
//
// Filter contract (per H.264 §8.7.2.4):
//   1. (m.x % pc.dst_stride_u8) ≥ 4   (kernel reads p3 at pix[-4])
//   2. pc.dst_stride_u8 = byte stride between rows
//   3. tc0_s pre-stored as signed int8 in m.z packed 4 bytes (one per
//      4-row segment along the 16-row edge)
//
// License: BSD-2-Clause.  Algorithm transcribed from
// tests/h264_h_loop_filter_luma_ref.c which mirrors FFmpeg
// ff_h264_h_loop_filter_luma_neon (LGPL-2.1+).

#version 450
#extension GL_EXT_shader_8bit_storage              : require
#extension GL_EXT_shader_explicit_arithmetic_types : require

layout(local_size_x = 256, local_size_y = 1, local_size_z = 1) in;

layout(binding = 0) readonly buffer Meta {
    uvec4 meta[];   // per edge: (dst_off, alpha|beta<<8, packed_tc0, _pad)
} u_meta;

layout(binding = 1) buffer Dst {
    uint8_t dst[];
} u_dst;

layout(push_constant) uniform PC {
    uint n_edges;
    uint dst_stride_u8;
    uint _pad0;
    uint _pad1;
} pc;

void main()
{
    uint gid          = gl_GlobalInvocationID.x;
    uint wg_id        = gl_WorkGroupID.x;
    uint lane_in_wg   = gid & 255u;
    uint edge_in_wg   = lane_in_wg >> 4;       // 0..15 (16 edges/WG)
    uint row_in_edge  = lane_in_wg & 15u;      // 0..15 — ROW along the V edge

    uint edge_idx = wg_id * 16u + edge_in_wg;
    if (edge_idx >= pc.n_edges) return;

    uvec4 m = u_meta.meta[edge_idx];
    uint stride = pc.dst_stride_u8;
    // dst_off addresses row 0 col 0 of the right block; advance by row * stride
    // to land at this lane's row.  The kernel reads pix[-4..+3] AT THIS ROW.
    uint dst_off = m.x + row_in_edge * stride;
    int alpha = int(m.y & 0xffu);
    int beta  = int((m.y >> 8) & 0xffu);

    // tc0 segment = 0..3 indexed by (row_in_edge / 4).
    uint seg = row_in_edge >> 2;
    uint tc0_byte = (m.z >> (seg * 8u)) & 0xffu;
    int tc0_s = int(tc0_byte);
    if (tc0_s >= 128) tc0_s -= 256;

    if (alpha == 0 || beta == 0) return;
    if (tc0_s < 0) return;                     // segment skip

    // Horizontal access pattern — read cols at offsets [-3..+2] of this row.
    // p3 (col -4) unused in bS<4; same DCE comment as the V shader.
    int p2 = int(u_dst.dst[dst_off - 3u]);
    int p1 = int(u_dst.dst[dst_off - 2u]);
    int p0 = int(u_dst.dst[dst_off - 1u]);
    int q0 = int(u_dst.dst[dst_off       ]);
    int q1 = int(u_dst.dst[dst_off + 1u]);
    int q2 = int(u_dst.dst[dst_off + 2u]);

    // Edge preconditions (same as V).
    if (abs(p0 - q0) >= alpha) return;
    if (abs(p1 - p0) >= beta)  return;
    if (abs(q1 - q0) >= beta)  return;

    int ap = abs(p2 - p0);
    int aq = abs(q2 - q0);
    bool ap_lt = ap < beta;
    bool aq_lt = aq < beta;
    int tc = tc0_s + int(ap_lt) + int(aq_lt);

    int delta = clamp(((q0 - p0) * 4 + (p1 - q1) + 4) >> 3, -tc, tc);
    int p0p = clamp(p0 + delta, 0, 255);
    int q0p = clamp(q0 - delta, 0, 255);

    int p1p = p1;
    if (ap_lt) {
        int d_p1 = clamp((p2 + ((p0 + q0 + 1) >> 1) - 2*p1) >> 1, -tc0_s, tc0_s);
        p1p = clamp(p1 + d_p1, 0, 255);
    }
    int q1p = q1;
    if (aq_lt) {
        int d_q1 = clamp((q2 + ((p0 + q0 + 1) >> 1) - 2*q1) >> 1, -tc0_s, tc0_s);
        q1p = clamp(q1 + d_q1, 0, 255);
    }

    u_dst.dst[dst_off - 2u] = uint8_t(p1p);
    u_dst.dst[dst_off - 1u] = uint8_t(p0p);
    u_dst.dst[dst_off       ] = uint8_t(q0p);
    u_dst.dst[dst_off + 1u] = uint8_t(q1p);
}