claude-noether
3db059ffab
Ports cycle 8's v3d_h264deblock.comp (V edge, horizontal across a row)
to the H orientation (V edge, horizontal across a column). Same
algorithm, transposed access pattern:
V variant: lane → column, reads/writes pix[±N*stride] (vertical I/O)
H variant: lane → row, reads/writes pix[±N] (horizontal I/O)
WG geometry unchanged: 256 invocations, 16 edges/WG, 16 lanes/edge.
Lane-in-edge interpretation flips: column-index for V → row-index
for H. tc0 segment math unchanged (one tc0 byte per 4 lanes).
dst_max calculation flips: V used dst_off + 3*stride + 16 (cols),
H uses dst_off + 15*stride + 4 (rows).
Recipe table: DAEDALUS_KERNEL_H264_DEBLOCK_LH = QPU (was CPU). AUTO
dispatch now picks QPU for the H edge as well as the V edge. CPU
NEON path stays as the explicit-SUBSTRATE_CPU + has_qpu=0 fallback.
Verified on hertz (Pi 5 / V3D 7.1):
$ ./build/test_api_h264 | grep luma_h
H264_DEBLOCK_LH recipe substrate: 2 (was 1 — flipped to QPU)
H.264 deblock luma h: 1024/1024 bytes bit-exact (100.0000%)
Bit-exact against the C reference (h264_h_loop_filter_luma_ref) on
8 tiles × 8 cols × 16 rows of random input. Same correctness gate
as the cycle 8 V shader.
CMake plumbing: glslang rule for v3d_h264deblock_h.comp; new SPV
added to daedalus_shaders ALL list + install rule. daedalus_ctx
gains a parallel h264deblock_h_pipe_ready / h264deblock_h_pipe pair
(can't share with V because pipelines bind a specific SPIR-V module
at create time).
What this changes for the substitution arc: PR #97's 0008-h264-
deblock-luma-h substitution patch already plumbed
daedalus_recipe_dispatch_h264_deblock_luma_h through libavcodec.
That path was NEON-by-recipe; with this PR it becomes QPU-by-recipe
(unless the libavcodec ctx is no-QPU per daedalus_ctx_create_no_qpu,
in which case it stays NEON — same shape as cycle 8's V shader).
Coverage state for H.264 8-bit 4:2:0 deblock kernels (QPU shaders):
luma_v ✓ cycle 8 ✓ now
luma_h — ✓ THIS PR
chroma_v/h — (CPU NEON; smaller tiles, lower-priority)
*_intra (4) — (CPU NEON; less common)
112 lines
4.0 KiB
Plaintext
112 lines
4.0 KiB
Plaintext
// daedalus-fourier — H.264 luma "h_loop_filter" (horizontal filtering
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// across a vertical edge), non-intra bS<4 variant. Sibling of cycle 8's
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// v3d_h264deblock.comp; same algorithm with row/col access transposed.
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//
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// V3D 7.1 via Mesa v3dv compute. Same WG geometry as the V shader:
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// - 256 invocations / WG, 16 edges/WG (16 lanes/edge = 1 sg/edge)
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// - uint8_t dst SSBO via storageBuffer8BitAccess
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// - No barrier (each lane independent)
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// - lane_in_edge = ROW index (0..15) along the vertical edge
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// - meta.dst_off points to (row 0, col 0) of the RIGHT block;
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// the kernel reads cols [-4..+3] of each row and writes [-2..+1].
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//
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// Filter contract (per H.264 §8.7.2.4):
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// 1. (m.x % pc.dst_stride_u8) ≥ 4 (kernel reads p3 at pix[-4])
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// 2. pc.dst_stride_u8 = byte stride between rows
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// 3. tc0_s pre-stored as signed int8 in m.z packed 4 bytes (one per
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// 4-row segment along the 16-row edge)
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//
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// License: BSD-2-Clause. Algorithm transcribed from
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// tests/h264_h_loop_filter_luma_ref.c which mirrors FFmpeg
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// ff_h264_h_loop_filter_luma_neon (LGPL-2.1+).
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#version 450
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#extension GL_EXT_shader_8bit_storage : require
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#extension GL_EXT_shader_explicit_arithmetic_types : require
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layout(local_size_x = 256, local_size_y = 1, local_size_z = 1) in;
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layout(binding = 0) readonly buffer Meta {
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uvec4 meta[]; // per edge: (dst_off, alpha|beta<<8, packed_tc0, _pad)
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} u_meta;
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layout(binding = 1) buffer Dst {
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uint8_t dst[];
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} u_dst;
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layout(push_constant) uniform PC {
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uint n_edges;
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uint dst_stride_u8;
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uint _pad0;
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uint _pad1;
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} pc;
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void main()
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{
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uint gid = gl_GlobalInvocationID.x;
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uint wg_id = gl_WorkGroupID.x;
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uint lane_in_wg = gid & 255u;
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uint edge_in_wg = lane_in_wg >> 4; // 0..15 (16 edges/WG)
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uint row_in_edge = lane_in_wg & 15u; // 0..15 — ROW along the V edge
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uint edge_idx = wg_id * 16u + edge_in_wg;
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if (edge_idx >= pc.n_edges) return;
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uvec4 m = u_meta.meta[edge_idx];
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uint stride = pc.dst_stride_u8;
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// dst_off addresses row 0 col 0 of the right block; advance by row * stride
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// to land at this lane's row. The kernel reads pix[-4..+3] AT THIS ROW.
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uint dst_off = m.x + row_in_edge * stride;
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int alpha = int(m.y & 0xffu);
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int beta = int((m.y >> 8) & 0xffu);
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// tc0 segment = 0..3 indexed by (row_in_edge / 4).
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uint seg = row_in_edge >> 2;
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uint tc0_byte = (m.z >> (seg * 8u)) & 0xffu;
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int tc0_s = int(tc0_byte);
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if (tc0_s >= 128) tc0_s -= 256;
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if (alpha == 0 || beta == 0) return;
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if (tc0_s < 0) return; // segment skip
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// Horizontal access pattern — read cols at offsets [-3..+2] of this row.
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// p3 (col -4) unused in bS<4; same DCE comment as the V shader.
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int p2 = int(u_dst.dst[dst_off - 3u]);
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int p1 = int(u_dst.dst[dst_off - 2u]);
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int p0 = int(u_dst.dst[dst_off - 1u]);
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int q0 = int(u_dst.dst[dst_off ]);
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int q1 = int(u_dst.dst[dst_off + 1u]);
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int q2 = int(u_dst.dst[dst_off + 2u]);
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// Edge preconditions (same as V).
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if (abs(p0 - q0) >= alpha) return;
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if (abs(p1 - p0) >= beta) return;
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if (abs(q1 - q0) >= beta) return;
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int ap = abs(p2 - p0);
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int aq = abs(q2 - q0);
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bool ap_lt = ap < beta;
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bool aq_lt = aq < beta;
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int tc = tc0_s + int(ap_lt) + int(aq_lt);
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int delta = clamp(((q0 - p0) * 4 + (p1 - q1) + 4) >> 3, -tc, tc);
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int p0p = clamp(p0 + delta, 0, 255);
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int q0p = clamp(q0 - delta, 0, 255);
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int p1p = p1;
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if (ap_lt) {
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int d_p1 = clamp((p2 + ((p0 + q0 + 1) >> 1) - 2*p1) >> 1, -tc0_s, tc0_s);
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p1p = clamp(p1 + d_p1, 0, 255);
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}
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int q1p = q1;
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if (aq_lt) {
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int d_q1 = clamp((q2 + ((p0 + q0 + 1) >> 1) - 2*q1) >> 1, -tc0_s, tc0_s);
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q1p = clamp(q1 + d_q1, 0, 255);
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}
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u_dst.dst[dst_off - 2u] = uint8_t(p1p);
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u_dst.dst[dst_off - 1u] = uint8_t(p0p);
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u_dst.dst[dst_off ] = uint8_t(q0p);
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u_dst.dst[dst_off + 1u] = uint8_t(q1p);
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}
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