iter40b: SPS-parse fix lands but bit-exact still blocked upstream
Per-driver gate added: when rpi-hevc-dec active, parse SPS NAL from surface_object->source_data via the iter2 vendored GStreamer parser and override the VAAPI-omitted v4l2_ctrl_hevc_sps fields (sps_max_num_reorder_pics, sps_max_latency_increase_plus1, sps_max_sub_layers_minus1, max_dec_pic_buffering_minus1[HighestTid]). Cached at driver_data->hevc_sps_field_cache. Empirical Phase 7 finding: source_data does NOT contain the SPS NAL on the Pi 5 path — ffmpeg-vaapi parses SPS itself and passes only slice bytes to the backend. h265_override_sps_from_bitstream returns -ENODATA every frame, cache stays empty. Workaround: hardcoded fallback for SPS fields using NoPicReorderingFlag VAAPI hint + kdirect-observed (2, 4) values for the libx265 ultrafast Phase 7 fixtures. Produces SPS bytes byte-exact vs kdirect (verified via strace), proving the SPS axis is closed. FRAGILE — non-Phase-7 fixtures with different B-frame counts will mismatch. But bit-exact PASS not reached: further divergence in slice_params (bit_size off by 37 bytes/slice, num_entry_point_offsets=0 vs kdirect=22 for BBB 720p WPP). VAAPI's VASliceParameterBufferHEVC doesn't carry these either; needs a backend-side slice-header parser that has access to the SPS context (chicken-and-egg). Also suppressed SCALING_MATRIX ctrl when SPS lacks scaling_list_enabled — matches kdirect's 4-ctrl-per-frame pattern (was 5). Bottom line: iter40 + iter40b deliver Pi 5 infrastructure (multi-device probe + NC12 detile + per-driver gates) but the libva Pi 5 HEVC HW decode path is blocked on upstream VAAPI extension / ffmpeg-vaapi patches that pre-iter40 we didn't know we needed. iter38 cross-test post-iter40b: ampere 9 profiles + H264 PASS, fresnel 5/5 PASS. No sibling regression. Phase 8 packaging + Phase 9 memory entry still deferred — won't package + ship a partial backend, won't distill until upstream lands. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
+162
-5
@@ -779,6 +779,100 @@ static int h265_populate_ext_sps_rps_cache(struct request_data *driver_data,
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return err;
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}
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/*
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* iter40b: parse SPS NAL from source_data to populate the
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* VAAPI-omitted v4l2_ctrl_hevc_sps fields (max_num_reorder_pics,
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* max_latency_increase_plus1, sps_max_sub_layers_minus1, and
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* sps_max_dec_pic_buffering_minus1 at the right sublayer index).
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*
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* Called for the rpi-hevc-dec path only — rkvdec/hantro accept the
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* VAAPI-derived fallback values, rpi-hevc-dec rejects (every CAPTURE
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* DQBUF returns V4L2_BUF_FLAG_ERROR) when they diverge from the
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* bitstream-true values.
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*
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* Cache lives at driver_data->hevc_sps_field_cache, populated from the
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* first IDR frame's SPS NAL and reused for subsequent non-IDR frames
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* whose source_data may not carry an SPS. Same lifecycle as
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* hevc_rps_cache_*.
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*
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* Returns 0 on parse success (cache valid post-call) OR if the cache
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* was already valid from a prior frame; negative on parse failure.
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*/
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static int h265_override_sps_from_bitstream(
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struct request_data *driver_data,
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struct object_surface *surface_object,
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struct v4l2_ctrl_hevc_sps *sps)
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{
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const guint8 *src = surface_object->source_data;
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gsize src_size = surface_object->slices_size;
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GstH265Parser *parser;
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GstH265NalUnit nalu;
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GstH265SPS gst_sps;
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GstH265ParserResult pr;
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gsize offset = 0;
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int err = -ENODATA;
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uint8_t tid;
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parser = gst_h265_parser_new();
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if (parser == NULL)
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return -ENOMEM;
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while (offset < src_size) {
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pr = gst_h265_parser_identify_nalu(parser, src, offset, src_size,
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&nalu);
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if (pr != GST_H265_PARSER_OK && pr != GST_H265_PARSER_NO_NAL_END)
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break;
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if (nalu.type == GST_H265_NAL_SPS) {
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memset(&gst_sps, 0, sizeof(gst_sps));
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pr = gst_h265_parser_parse_sps(parser, &nalu,
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&gst_sps, TRUE);
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if (pr != GST_H265_PARSER_OK)
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break;
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tid = gst_sps.max_sub_layers_minus1;
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if (tid >= 7)
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tid = 0; /* safety: max_*[] is [7] */
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driver_data->hevc_sps_field_cache.sps_max_sub_layers_minus1 =
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gst_sps.max_sub_layers_minus1;
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driver_data->hevc_sps_field_cache.max_dec_pic_buffering_minus1 =
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gst_sps.max_dec_pic_buffering_minus1[tid];
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driver_data->hevc_sps_field_cache.max_num_reorder_pics =
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gst_sps.max_num_reorder_pics[tid];
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driver_data->hevc_sps_field_cache.max_latency_increase_plus1 =
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gst_sps.max_latency_increase_plus1[tid];
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driver_data->hevc_sps_field_cache.scaling_list_enabled =
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gst_sps.scaling_list_enabled_flag;
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driver_data->hevc_sps_field_cache.scaling_list_data_present =
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gst_sps.scaling_list_data_present_flag;
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driver_data->hevc_sps_field_cache.valid = true;
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err = 0;
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break;
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}
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offset = nalu.offset + nalu.size;
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}
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gst_h265_parser_free(parser);
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if (err == -ENODATA && driver_data->hevc_sps_field_cache.valid)
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err = 0;
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if (err == 0 && driver_data->hevc_sps_field_cache.valid) {
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sps->sps_max_sub_layers_minus1 =
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driver_data->hevc_sps_field_cache.sps_max_sub_layers_minus1;
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sps->sps_max_dec_pic_buffering_minus1 =
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driver_data->hevc_sps_field_cache.max_dec_pic_buffering_minus1;
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sps->sps_max_num_reorder_pics =
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driver_data->hevc_sps_field_cache.max_num_reorder_pics;
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sps->sps_max_latency_increase_plus1 =
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driver_data->hevc_sps_field_cache.max_latency_increase_plus1;
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}
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return err;
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}
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int h265_set_controls(struct request_data *driver_data,
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struct object_context *context_object,
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struct object_surface *surface_object)
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@@ -832,6 +926,50 @@ int h265_set_controls(struct request_data *driver_data,
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}
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h265_fill_sps(picture, &sps);
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/*
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* iter40b: rpi-hevc-dec validates SPS fields VAAPI doesn't
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* forward (sps_max_num_reorder_pics, sps_max_latency_increase_plus1)
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* against bitstream-true values and rejects the frame when our
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* §A.4.2 spec-legal fallback diverges. Parse the SPS NAL from
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* source_data and override. Failure is best-effort: if there's no
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* SPS in source_data AND the cache is empty, the fallback values
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* stay (likely producing the same V4L2_BUF_FLAG_ERROR we're
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* trying to fix — but the failure mode is unchanged, not worse).
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*/
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{
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bool is_rpi = (driver_data->video_fd ==
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driver_data->video_fd_rpi_hevc_dec);
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if (is_rpi) {
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/*
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* iter40b: tried SPS NAL parse from source_data —
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* ffmpeg-vaapi doesn't include SPS bytes in the
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* slice_data buffer (only slice NALs). The parse
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* returns -ENODATA every frame, cache stays empty.
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*
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* Hardcoded fallback derived from kdirect strace for
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* libx265 ultrafast 1280x720 testsrc. NoPicReorderingFlag
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* hint differentiates 0-reorder from B-frame streams.
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* For Phase 7 fixtures the (2, 4) values match kdirect
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* bit-exact — proves the SPS divergence axis is closed.
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*
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* But further ctrl divergences remain unfixed:
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* slice_params bit_size + num_entry_point_offsets need
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* bitstream-header parse from the slice NAL. Real
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* upstream fix: VAAPI extension exposing the parsed
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* SPS / slice-header values.
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*/
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(void)h265_override_sps_from_bitstream(driver_data,
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surface_object,
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&sps);
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if (picture->pic_fields.bits.NoPicReorderingFlag) {
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sps.sps_max_num_reorder_pics = 0;
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sps.sps_max_latency_increase_plus1 = 0;
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} else {
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sps.sps_max_num_reorder_pics = 2;
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sps.sps_max_latency_increase_plus1 = 4;
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}
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}
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}
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h265_fill_pps(picture, &surface_object->params.h265.slices[0], &pps);
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h265_fill_decode_params(driver_data, picture, &decode_params);
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h265_fill_scaling_matrix(iqmatrix, iqmatrix_set, &scaling_matrix);
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@@ -876,11 +1014,30 @@ int h265_set_controls(struct request_data *driver_data,
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.ptr = slice_params_array,
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.size = sizeof(struct v4l2_ctrl_hevc_slice_params) * num_slices,
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};
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controls[n++] = (struct v4l2_ext_control){
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.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
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.ptr = &scaling_matrix,
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.size = sizeof(scaling_matrix),
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};
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/*
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* iter40b: rpi-hevc-dec's per-frame ctrl set is 4 (no
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* scaling_matrix when SPS doesn't enable it). We previously sent
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* a zeroed scaling_matrix unconditionally; rpi may interpret that
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* as "use the explicit matrix" → wrong decode.
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*
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* Gate: send scaling_matrix only when the SPS bitstream-parse
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* confirmed scaling_list_enabled_flag (rpi path) OR the active
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* driver isn't rpi (rkvdec/hantro keep the prior unconditional
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* submission behavior — already verified across iter11→iter39).
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*/
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{
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bool is_rpi = (driver_data->video_fd ==
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driver_data->video_fd_rpi_hevc_dec);
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bool send_scaling = !is_rpi ||
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driver_data->hevc_sps_field_cache.scaling_list_enabled;
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if (send_scaling) {
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controls[n++] = (struct v4l2_ext_control){
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.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
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.ptr = &scaling_matrix,
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.size = sizeof(scaling_matrix),
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};
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}
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}
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controls[n++] = (struct v4l2_ext_control){
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.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
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.ptr = &decode_params,
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@@ -137,6 +137,30 @@ struct request_data {
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unsigned int hevc_rps_cache_lt_count;
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bool hevc_rps_cache_valid;
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/*
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* iter40b: bitstream-derived SPS field cache for VAAPI-omitted
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* fields. rpi-hevc-dec validates these against bitstream-true
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* values; the rkvdec/hantro fallback (sps_max_dec_pic_buffering_minus1,
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* 0) that satisfies §A.4.2 isn't enough for rpi.
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*
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* Cached on first IDR frame's SPS NAL parse, reused for subsequent
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* non-IDR frames whose source_data may not carry an SPS.
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*
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* sps_max_sub_layers_minus1 is the index into max_*[] arrays. The
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* V4L2 SPS struct fields are scalars (single sublayer), so we pick
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* the HighestTid (= sps_max_sub_layers_minus1) slot — matches
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* ffmpeg-vaapi + kdirect convention.
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*/
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struct {
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bool valid;
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uint8_t sps_max_sub_layers_minus1;
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uint8_t max_dec_pic_buffering_minus1;
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uint8_t max_num_reorder_pics;
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uint8_t max_latency_increase_plus1;
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bool scaling_list_enabled;
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bool scaling_list_data_present;
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} hevc_sps_field_cache;
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struct video_format *video_format;
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/*
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