Live probe of rpi-hevc-dec on higgs (Pi CM5, kernel 6.12.75-rpt-rpi-2712,
Debian 13 trixie) answers Phase 0 open questions Q1, Q2, Q5, Q6
empirically; Q3 partial; Q4 still open.
Q1 (EXT_SPS): NOT present. Only standard V4L2_CID_STATELESS_HEVC_*.
Probe ctrl id 0xa97 returns EINVAL — same gate iter2's
has_hevc_ext_sps_rps_rkvdec uses. iter31 alpha-29 plumbing applies.
Q2 (hevc_start_code): default 0 "No Start Code"; matches our behaviour.
Q3 (NC12 SAND tile layout): partial. CAPTURE S_FMT for 1280x720 NC12
returns sizeimage=1382400 (linear NV12 byte count) but
bytesperline=1080 (suspect, encodes SAND col count not linear stride).
Need kernel-doc / driver-source read before writing detile primitive.
Q4 (DRM modifier round-trip): hwdownload rejects SAND-tiled drm_prime
(-38 Function not implemented). Backend CPU-detile to NV12 is the
safe path for Firefox.
Q5 (submission ordering): empirical ioctl trace shows canonical V4L2
stateless flow. Two notes for the backend: kdirect uses
V4L2_MEMORY_DMABUF for both queues (we use MMAP for CAPTURE on
rkvdec); kdirect does NOT need the iter25 SPS pre-seed pattern -
rpi-hevc-dec takes explicit NC12 + dims directly.
Q6 (packaging): Debian 13 trixie. Phase 8 needs a debian/ tree, not
just PKGBUILD. Decision in Phase 1.
Other findings: ffmpeg 7.1.3 from stock Debian is built with
--enable-v4l2-request. kdirect engagement line:
Hwaccel V4L2 HEVC stateless V4; devices: /dev/media1,/dev/video19;
buffers: src DMABuf, dst DMABuf; swfmt=rpi4_8
No libva ICD installed (only armada-drm_dri.so). mpv installable.
Firefox 145 + rpi-firefox-mods present.
Phase 0 closed. Phase 1 opens with goal:
HEVC bit-exact libva-vs-kdirect on higgs for 1280x720 Main 8-bit
via the new RPI_HEVC_DEC driver_kind slot + NC12 detile primitive.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
Empirical higgs probe (sibling session 2026-05-17) confirmed
rpi-hevc-dec at /dev/video19 is V4L2 STATELESS, not stateful:
- Section header literally "Stateless Codec Controls"
- OUTPUT V4L2_PIX_FMT_HEVC_SLICE (parsed slices), not full-stream HEVC
- V4L2_CID_STATELESS_HEVC_* control set + slice_param_array[4096]
- CAPTURE NC12 / NC30 (V4L2_PIX_FMT_NV12_COL128 / _10_COL128,
SAND 128-column tiled, Pi-specific)
So the Pi 5 HEVC HW path belongs HERE (request/stateless backend),
not in a separate stateful project. Replaces the now-deleted
libva-v4l2-stateful-fourier scaffold attempt.
phase0_pi5_hevc.md captures:
- Substrate (target host, backend baseline, empirical probe output)
- What carries forward unchanged (most of HEVC plumbing)
- What needs adding (RPI_HEVC_DEC driver_kind, NC12/NC30 video_format
+ detile primitive, image.c branch — small surface area)
- Six open questions Phase 1 must answer first (EXT_SPS presence,
start_code default, SAND tile spec, drm_prime modifier round-trip,
rpi-hevc-dec submission ordering quirks, packaging target OS)
- Phase 1 goal sketch (NOT locked) + Phase 3 baseline plan
No code in this commit. Phase 1 opens when higgs is up + first two
open questions are answered live.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
claude-noether