From: Markus Fritsche <mfritsche@reauktion.de>
Subject: [PATCH] arm64: dts: rockchip: rk3399-pinebook-pro: extend OPP tables with OC entries (1.704 / 2.184 GHz)

Inline the OPP-V2 cluster0 / cluster1 tables on the Pinebook Pro DTS to add
overclock points: cluster0 (A53) up to 1.704 GHz @ 1.175 V, cluster1 (A72)
up to 2.184 GHz @ 1.275 V.

Original tables (from rk3399.dtsi → cluster0/1_opp) are reused intact for
their points up to 1.416 / 1.800 GHz; the additional opp06 (cluster0) and
opp08 (cluster1) extend the curve. Voltages above the stock max follow the
community-validated PBP OC ladder; thermals on the Pinebook Pro chassis
sustain these without throttling for normal workloads.

The label match (`cluster0_opp`, `cluster1_opp`) means the DTC merges these
inline tables with the parent ones rather than treating them as new nodes.
opp00..opp05/07 have identical content to upstream; opp06/08 add the OC
points.

scope: board/pinebook-pro
fleet: fresnel

Signed-off-by: Markus Fritsche <mfritsche@reauktion.de>
---
 arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 78 ++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
@@ -18,6 +18,84 @@
 	compatible = "pine64,pinebook-pro", "rockchip,rk3399";
 	chassis-type = "laptop";

+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <750000 750000 1150000>;
+			clock-latency-ns = <40000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <825000 825000 1150000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <850000 850000 1150000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <900000 900000 1150000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <975000 975000 1150000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <1100000 1100000 1150000>;
+		};
+		opp06 {
+			opp-hz = /bits/ 64 <1704000000>;
+			opp-microvolt = <1175000 1175000 1175000>;
+		};
+	};
+
+	cluster1_opp: opp-table-1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <750000 750000 1250000>;
+			clock-latency-ns = <40000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <800000 800000 1250000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <825000 825000 1250000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <850000 850000 1250000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <900000 900000 1250000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <1416000000>;
+			opp-microvolt = <975000 975000 1250000>;
+		};
+		opp06 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+		};
+		opp07 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+		};
+		opp08 {
+			opp-hz = /bits/ 64 <2184000000>;
+			opp-microvolt = <1275000 1275000 1275000>;
+		};
+	};
+
 	aliases {
 		mmc0 = &sdio0;
 		mmc1 = &sdmmc;