Diary: eDP analysis - power domain issue

DIARY.md

@@ -329,3 +329,88 @@ Entry (0x10978):
       ├─ Check result
       └─ Retry if failed
 ```
+
+## Day 2 Late Night Bonus: U-Boot eDP Analysis
+
+The user's GenBook eDP patches for U-Boot cause a boot hang. Without UART
+serial debug, the exact failure point was unknown. Here's the analysis from
+reading the patches:
+
+### Likely Failure Points (ordered by probability)
+
+**1. Missing Power Domain Enable (MOST LIKELY)**
+
+The RK3588 VOP2 and HDPTX PHY sit in the `pd_vo1` power domain. The VOP2
+driver (`rk3588_vop2.c`) **does not enable the power domain** — there's no
+`power_domain_on()` call in the probe function. If the VO1 power domain is
+off (which it is by default at boot), all register accesses to VOP2 and
+HDPTX PHY will **bus fault or return garbage**, hanging the SoC.
+
+The kernel driver handles this via the device tree `power-domains` property
+and the PM framework. U-Boot needs explicit power domain management.
+
+**Fix:** Add to VOP2 probe:
+```c
+struct power_domain pd;
+ret = power_domain_get(dev, &pd);
+if (!ret)
+    power_domain_on(&pd);
+```
+
+And ensure the DTS has:
+```dts
+&vop {
+    power-domains = <&power RK3588_PD_VOP>;
+};
+```
+
+**2. HDPTX PHY Poll Timeout Without Error Recovery**
+
+The PHY driver has three `regmap_read_poll_timeout` calls:
+- `PHY_RDY` — 5ms timeout
+- `PLL_LOCK_DONE` — 1ms timeout
+- `SB_RDY` — 1ms timeout
+
+If any of these times out (because the power domain is off or clocks aren't
+enabled), the driver prints an error but **continues execution**. Subsequent
+register writes to a non-responsive PHY could hang the bus.
+
+**Fix:** Return `-ETIMEDOUT` and abort initialization on poll failure.
+
+**3. Missing Clock Enable for HDPTX PHY**
+
+The HDPTX PHY probe function gets clocks and resets via DT, but the patch
+doesn't show explicit `clk_enable()` calls for the PHY reference clock.
+The kernel driver (`phy-rockchip-samsung-hdptx.c`) calls `clk_prepare_enable()`
+for `ref` and `apb` clocks. If these aren't enabled in U-Boot, the PHY
+PLL will never lock.
+
+**4. VOP2 DCLK Not Configured**
+
+The VOP2 driver gets `dclk` (display clock) but the pixel clock calculation
+and parent mux selection is complex on RK3588 (VPLL/CPLL/GPLL sources).
+If the clock tree isn't set up correctly, the VOP2 outputs nothing and the
+eDP link training fails.
+
+**5. DTS Overlay Issues**
+
+The U-Boot DTS overlay enables `edp1`, `hdptxphy1`, and `vop` but:
+- Doesn't set `power-domains` on any of them
+- Doesn't set clock assignments (`assigned-clocks`, `assigned-clock-rates`)
+- Uses `&vop` not `&vop2` (might not match the U-Boot DT node name)
+- Missing `edp1` status = "okay" (only sets panel, not status)
+
+### Debugging Strategy
+
+With the Tigard UART adapter (1.5Mbaud on UART2 debug pads):
+1. Enable `CONFIG_DEBUG_UART=y` and `CONFIG_LOG_MAX_LEVEL=9`
+2. Add `printf()` calls at VOP2 probe entry, PHY probe entry, and before
+   each poll timeout
+3. The hang point will be immediately visible in the serial output
+
+### Without UART (QEMU approach)
+
+Unlike the DDR blob, U-Boot is too complex for Unicorn emulation. But we
+can build U-Boot with `CONFIG_SANDBOX=y` on x86 and test the driver probe
+logic in the sandbox — this would catch null pointer dereferences and logic
+errors, though not hardware register issues.