Retract sibling's d328 register names — they addressed wrong sub-block

Previous commit committed sibling claims without verifying against
the TRM bit tables. Verification fails for d328:

  Sibling: +0x110 = CAL_RD_VWML0 (from TRM §2.4.3).
  Blob: writes 0xF000F000 to that offset.
  TRM: CAL_RD_VWML0 is READ-ONLY, bits[9:0]=rd_vwml0 code, [25:16]=rd_vwml1.
        Writing is a no-op.

Root cause of sibling's error: conflated 'DDRPHY_OPB + offset' with
d328's 'DDRPHY_OPB + 0x8000 + offset'. The +0x8000 sub-block is NOT
documented in the TRM; offsets 0x110/0x118/0x120/0x154/0x160/0x184
WITHIN that sub-block mean something different from CAL_RD_VWML0 etc.

Kept the TRM-verified names I DID check:
  - DDRCTL_DFISTAT @ +0x10514 (site 3)
  - DDRCTL_STAT @ +0x10014 (sites 2,4,5,7)
  - DDRPHY_SCHD_TRAIN_CON0 @ +0xa24 — bit layout verified directly

Retracted names for d328's +0x8XXX accesses; restoring the PHY_CTL_110
etc. RE-guess labels as the safe fallback. True names remain unknown
until we get hardware-trace data or the Synopsys DWC PUB databook.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

rk3588_regs_annotated.h

@@ -175,6 +175,15 @@
                                                             (TRM HIGH) */
 
 /* -------------------------------------------------------------------
+ * CORRECTION 2026-04-15 LATE EVENING:
+ *   The 'CAL_RD_VWML0' etc. names above apply to DDRPHY_OPB + small
+ *   offsets. d328's accesses are at DDRPHY_OPB + 0x8000 + small,
+ *   which is an UNDOCUMENTED sub-block of the DDRPHY space.
+ *   Writing 0xF000F000 to a TRM-documented READ-ONLY register
+ *   would be a no-op — contradicting the blob's actual behaviour —
+ *   so those names DO NOT apply here. The `PHY_CTL_110` etc.
+ *   heuristic labels (in the block above) are the safe fallback.
+ *
  * Semantic re-interpretation of FUN_0000d328 (train_phy_block):
  *   Writes 0x30003 to CAL_CON5 (+0x160):
  *     bit[0] wrtrn_cyc_mode=1  (low-freq edge mode)