From b8efa8f74228309344d6727cd3cad4ef1ed2df78 Mon Sep 17 00:00:00 2001
From: Markus Fritsche <fritsche.markus@gmail.com>
Date: Fri, 3 Apr 2026 23:48:00 +0200
Subject: [PATCH] OEM eDP analysis: force-hpd, power domains, clock parents

---
 DIARY.md | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/DIARY.md b/DIARY.md
index 7d8a9c5..8153d3d 100644
--- a/DIARY.md
+++ b/DIARY.md
@@ -414,3 +414,45 @@ Unlike the DDR blob, U-Boot is too complex for Unicorn emulation. But we
 can build U-Boot with `CONFIG_SANDBOX=y` on x86 and test the driver probe
 logic in the sandbox — this would catch null pointer dereferences and logic
 errors, though not hardware register issues.
+
+## Day 2 Final: OEM eDP Analysis — The Missing Pieces
+
+Analyzing the OEM CoolPi SPI image (genbook_spi.img) from /rpool/nas revealed
+exactly what the working eDP init looks like vs our broken patches:
+
+### OEM DTS vs Our Patches — The Differences
+
+| Property | OEM (working) | Our patch (broken) |
+|----------|--------------|-------------------|
+| VOP power-domain | `<&power 0x18>` (PD_VOP) | **MISSING** |
+| eDP power-domain | `<&power 0x1A>` (PD_VO1) | **MISSING** |
+| eDP `force-hpd` | **present** | **MISSING** |
+| eDP clocks | `dp`, `pclk` explicit | inherited from kernel DTS |
+| VOP `assigned-clocks` | CPLL parent for ACLK | **MISSING** |
+| VOP `rockchip,pmu` | present | **MISSING** |
+| HDPTX PHY resets | 4 resets explicit | inherited |
+| edp1 (0xfded0000) | `status = "okay"` | Was missing (fixed in 0009) |
+
+### Key Findings
+
+1. **`force-hpd` is critical** — eDP panels don't have hot-plug detect.
+   Without `force-hpd`, the eDP driver waits for HPD assertion which never
+   comes on an internal laptop panel. This alone could cause a hang.
+
+2. **VOP power domain is 0x18 (PD_VOP)**, eDP power domain is 0x1A (PD_VO1).
+   These are DIFFERENT power domains. Our fix patch only added power domain
+   to VOP2, not to the eDP controller node.
+
+3. **`assigned-clocks` sets CPLL as ACLK parent** — this is the VOP AXI clock
+   parent mux. Without this, the VOP2 might run off the wrong clock source.
+
+4. **OEM uses edp@fded0000 (eDP1)** not edp@fdec0000 (eDP0). Our DTS
+   correctly targets `&edp1`. Good.
+
+### Updated Fix Required
+
+The 0009 patch needs to add:
+- `force-hpd` to edp1 node
+- `power-domains` to edp1, vop, and hdptxphy1
+- `assigned-clocks`/`assigned-clock-parents` to vop
+- `rockchip,pmu` phandle to vop