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BUG_ANALYSIS + regs_annotated.h: TRM-canonical names for poll-site regs

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Per RK3588 TRM Part 2 chapter 2 (DMC, 522 pages):
  +0x10080 = DDRCTL_MRCTRL0   (Mode Register Control, was MicroReset)
  +0x10090 = DDRCTL_MRSTAT    (MR Status mr_wr_busy, was MicroContMuxSel)
  +0x10514 = DDRCTL_DFISTAT   (DFI Status dfi_init_complete, was UctWriteProtShadow)

These are uMCTL2 controller registers — Rockchip-documented — NOT the
opaque PHY firmware scratch regs our 2026-04 analysis guessed. Poll
semantics now vendor-grounded: wait for MR command roundtrip, wait
for PHY-side DFI handshake.

Low-offset polls in train_phy_block (0x110, 0x118, 0x120, 0x154, 0x160,
0x184) plus the 0x684/0xa24/0xb88 ones remain DWC PUB and thus
undocumented; kept the best-effort RE names with `(RE)` tag in the
BUG_ANALYSIS table so a reader can tell which ones are vendor-canonical
and which are guesses.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
Markus Fritsche
2026-04-15 08:38:49 +02:00
parent 5aef5bd118
commit e30127d056
2 changed files with 65 additions and 10 deletions
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rk3588_regs_annotated.h
+40
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@@ -82,3 +82,43 @@
/* === SRAM (0xFF000000) === */
#define _DAT_ff000010 REG32(0xFF000010) /* SRAM: boot flag/mailbox */
/* =====================================================================
* TRM-CANONICAL names for poll-site registers (RK3588 TRM Part 2 Ch.2)
* Added 2026-04-15 after cross-referencing the 522-page DMC chapter.
* Offsets are within a DDRCTL (uMCTL2) per-channel base.
* =====================================================================
*/
#define DDRCTL_MRCTRL0 0x10080 /* Mode Register Control 0
- mr_wr[31]: write a MR command
- mr_addr[23:16]: MR address
- mr_data[15:0]: MR data to write
Previously guessed as "MicroReset". */
#define DDRCTL_MRSTAT 0x10090 /* Mode Register Status
- mr_wr_busy[0]: 1 while MR cmd in flight
Poll: WAIT for bit 0 == 0.
Previously guessed as "MicroContMuxSel". */
#define DDRCTL_DFISTAT 0x10514 /* DFI Status
- dfi_init_complete[0]: 1 when PHY ready
Poll: WAIT for bit 0 == 1.
Previously guessed as "UctWriteProtShadow". */
/* Low-offset polls in FUN_0000d328 (train_phy_block) and friends are
* Synopsys DWC PUB registers — NOT in RK3588 TRM. Still require RE.
* The heuristic labels below come from the d328 analysis (2026-04-15):
*/
#define PHY_OFF_BASE 0x8000 /* sub-block offset within a PHY used by d328 */
#define PHY_CTL_110 0x110 /* write 0xF000F000 to trigger step, 0xF0000000 to clear */
#define PHY_STAT_A_118 0x118 /* wait for bits[31:28] != 0 */
#define PHY_STAT_B_120 0x120 /* wait for bits[31:28] != 0 */
#define PHY_CFG_A_154 0x154 /* write 0x30003 (go), 0x30000 (end) */
#define PHY_CFG_B_160 0x160 /* write 0x30003 (go), 0x30000 (end) */
#define PHY_HANDSHAKE_184 0x184 /* wait for bits[1:0] non-zero, then zero */
/* The large-offset polls (0xb88, 0xa24, 0x684) in the early-cluster
* functions are also DWC PUB; semantic guesses in BUG_ANALYSIS.md. */