TRM Part 2 chapter 2 (DMC, 522 pages) reveals the offsets we poll at
+0x10080/+0x10090/+0x10514 are NOT PHY firmware scratch regs as our
earlier analysis guessed. They are uMCTL2 controller registers:
+0x10080 = DDRCTL_MRCTRL0 (Mode Register Control)
+0x10090 = DDRCTL_MRSTAT (Mode Register Status — wait for MR complete)
+0x10514 = DDRCTL_DFISTAT (DFI Status — wait for PHY handshake)
Semantics are now grounded in vendor docs instead of educated guesses.
The PHY-side polls (0x110, 0x118, 0x184 etc. in d328) remain
undocumented — TRM does not republish the Synopsys DWC PUB register
map. Still need RE for those.
TRM cached at boltzmann:~/projects/AMPere/vendor/trm/ (pdf + txt).
Fetched via Stanford mirror (surfaced by the Chinese-language research
sibling alongside rk-open-docs, mfkiwl/rk-open-docs which has Rockchip
internal DDR docs for RK322x..RK1808 era — Innosilicon PHY, not our
DWC multiPHY, so useful for methodology but not direct reference).
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
