2c2
< // Source: rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.19.bin
---
> // Source: rk3588_ddr_lp4_1848MHz_lp5_2112MHz_v1.19.bin
78c78
<       FUN_000104b8(s_DDR_ff1a08bde6_typ_25_03_13_15_3_00010d6c);
---
>       FUN_000104b8(s_DDR_ff1a08bde6_typ_25_04_21_14_3_00010d6c);
11841c11841
<       FUN_000104b8(s_DDR_ff1a08bde6_typ_25_03_13_15_3_00010d6c);
---
>       FUN_000104b8(s_DDR_ff1a08bde6_typ_25_04_21_14_3_00010d6c);