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test0r 816848a474 RK3588 DDR init blob reverse engineering 
- Ghidra decompilation of v1.02-v1.19 blobs (118 functions)
- 53 functions renamed, 79 MMIO registers mapped to TRM
- 45 timeout-less poll loops identified and patched
- Production patcher (patch_prod.py) and QEMU emulator
- Comprehensive analysis, frequency tables, community research

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
2026-04-03 13:06:47 +02:00

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I'll conduct thorough web research across all three areas simultaneously. Let me start with broad searches and then dig into specifics. Good initial results. Now let me dig deeper into specific areas. Excellent - the ddrbin_tool user guide is very informative. Now let me dig into the eyescan specifics, SkatterBencher overclocking articles, and more technical forum threads. Now I have a key finding: the 2736MHz LP5 config was dropped in v1.16 in favor of 2400MHz. Let me dig deeper into that and the Armbian/Radxa community specifics. I now have enough information to write a comprehensive report. Let me do a few final targeted searches to fill remaining gaps. I now have comprehensive information across all three topic areas. Let me compile the full technical report.

DDR PHY Training for LPDDR5 / RK3588: Comprehensive Technical Report

Part 1: DDR PHY Training Fundamentals for LPDDR5

Why Training Exists at All

At LPDDR5 data rates (up to 6400 Mbps, i.e., 3200 MHz DDR clock), a signal UI (Unit Interval) is about 156 ps. PCB trace-length variations of even a few millimetres, silicon process variation in the PHY's CMOS delay cells, and on-die termination (ODT) resistors that drift with temperature and voltage — all produce timing offsets that are a significant fraction of that UI. Without calibration, bit errors occur. Training sweeps delay-line taps and VREF levels, finds the noise-free eye centre, and programs those found values into the PHY's configuration registers.

Because the trained values are held in volatile SRAM inside the PHY (not flash/eFuse), and because the optimum operating point drifts with temperature and supply voltage (CMOS characteristics are well-known functions of both), training must run from scratch every cold boot. During operation, periodic re-training runs in the background (via BL31 on RK3588) to compensate for runtime temperature drift.

LPDDR5 Architecture Differences That Make Training Harder

LPDDR5 introduces a separate WCK (Write Clock) signal from the host that is distinct from the CK command clock. WCK runs at 2x or 4x CK frequency (the CKR — Clock Ratio — modes), up to 3200 MHz. DQ data is clocked by WCK on writes; on reads the DRAM generates RDQS from WCK and pushes it back to the host alongside DQ. This decoupled clocking adds additional training steps absent from LPDDR4:

  • The DRAM requires internal WCK-to-CK synchronisation before it can do anything at all (WCK2CK synchronisation protocol: at least 1 static CK, then half-rate activity, then full-rate activity).
  • The PHY must separately level WCK vs CK (WCK2CK leveling), then align WCK relative to each DQ bit (WCK2DQ training), then separately gate/align the incoming RDQS from the DRAM.

The Full LPDDR5 Training Sequence

1. ZQ Calibration (Impedance Calibration)

Not strictly "training" in the DDR sense but is always first. The PHY drives a precision resistor on the ZQ pad to calibrate its on-die pull-up and pull-down transistors to the correct drive impedance (typically 240Ω external reference → 40Ω DQ, 80Ω differential DQS). This affects all subsequent signal integrity. The result is stored in the PHY's ZQ calibration registers. CMOS resistance varies ±20% PVT (process, voltage, temperature), making this mandatory every boot.

2. CA Training — Command Bus Training (CBT Mode 1 and Mode 2)

Purpose: The CA (Command/Address) bus runs from SoC to DRAM at CK rate (up to 1600 Mbps). Parasitic capacitance, trace skew, and CMOS process variation create a CA-to-CK timing offset at the DRAM's input. CA training centres each CA bit on the CK rising edge.

Mode 1: The DRAM is put into CA training mode (via MR13 register) and mirrors received CS/CA patterns back on DQ[7:0]. The PHY iterates phase-interpolator delays on the CA bus, reads the returned pattern, finds the transition points (fail→pass, pass→fail), and centres the CA delay at the midpoint of the pass window.

Mode 2: Extends Mode 1 by also training VREF(CA) — the reference voltage the DRAM uses to distinguish logic 0 from 1 on the CA input. Mode 2 requires the DMI pin. By sweeping both delay and VREF simultaneously (a 2D sweep), the PHY finds the centre of the 2D pass region for CA. The result is written to the DRAM via MR12 (VREF(CA) setting, bits OP[6:0]).

Host side: The PHY's own VREF for driving CA (not a training result per se — the host drives into the DRAM's input, which has its own VREF).

3. WCK2CK Leveling

Purpose: The WCK high-speed write clock (running at 2x or 4x CK) is a separate signal. The PHY adjusts its WCK output delay so that WCK edges align correctly with CK inside the DRAM. The DRAM reports the alignment status via DQ feedback. This is essentially write-leveling for the WCK signal.

4. Write Leveling

Purpose (general, inherited from DDR3+): The DQS strobe must arrive at the DRAM aligned with the CK edge. With point-to-point LPDDR5 topology, each channel's DQS traces have different lengths from the controller. Write leveling corrects the DQS-to-CK skew per byte lane.

Mechanism: PHY drives DQS as a strobe; DRAM samples CK on that DQS edge and returns the sampled value on DQ. PHY sweeps DQS output delay until CK transitions 0→1 are seen on DQ, then backs up to the 0→1 crossing point. Result: DQS leading edge is time-aligned with CK at the DRAM's input.

In LPDDR5, this also applies to the WCK strobe for write data (WCK2CK leveling above subsumes part of this), and the separate RDQS for read data.

5. Read Gate Training (RDQS Gate Training)

Purpose: On reads, the DRAM sends RDQS back to the host, but RDQS has a variable propagation delay (board trace + DRAM output delay). The PHY's read gate must open exactly when RDQS arrives; if it opens too early it captures noise, too late it misses the preamble.

Mechanism: The PHY sends a read command, sweeps its internal gate delay, and detects when RDQS toggles appear at the gate output without using DQ data (RDQS toggle detection). The gate delay is set to the midpoint of the valid window.

This is one of the most sensitive training steps because LPDDR5 preambles are shorter and RDQS frequencies are higher (up to 3200 MHz) than previous generations.

6. WCK-DQ Training (Write DQ Deskew)

Purpose: Even within a byte lane, each DQ bit can have slightly different trace delays or capacitive loading. WCK-DQ training aligns all DQ bits of a lane to each other relative to WCK.

Mechanism: A known pattern is written using each DQ bit independently, and fine-grained delay-line taps (BDL — Bit Delay Line) for each individual DQ bit are swept until all bits align. The PHY's per-bit delay lines (typically 8 delay taps per bit in Synopsys DWC implementations) are adjusted independently.

7. Read DQ Per-Bit Deskew and Centering

Purpose: On reads, each of the 8 DQ bits in a byte lane arrives at the PHY at slightly different times relative to RDQS, due to trace skew and DRAM output variation. Per-bit deskew first aligns each DQ bit to the "slowest" bit in the byte, expanding the effective eye per-bit. Then eye centering places RDQS at the center of the combined eye.

Mechanism (1D — timing only): PHY sweeps BDL delay for each DQ bit, writes a known pattern, reads back, and records pass/fail for each delay setting. The pass window center is the optimal BDL setting for that bit. RDQS is then placed at the center of the resulting eye across all 8 bits.

8. Write Eye Training / Read Eye Training (2D Training)

Purpose: 1D training only finds the timing center. 2D training simultaneously sweeps voltage (VREF) and timing (delay), mapping the full 2D pass region (the "eye" in voltage-timing space). The 2D eye center provides larger margins against both timing jitter and voltage noise.

Mechanism: For each VREF step (from PHY-side or DRAM-side VREF registers), the delay-line sweep is repeated. This produces a grid of pass/fail data. The 2D centroid is computed and that (timing, VREF) point is programmed.

This is computationally expensive — the Synopsys DWC PHY firmware runs 1D first, then 2D, as separate stages. 2D eye results are what the RK3588's eyescan blob captures and visualises.

9. VREF Training — Host Side and DRAM Side

VREF is the DC reference voltage that separates logic 0 from 1 at the receiver input.

DRAM-side VREF for DQ (read VREF): The host writes a pattern, the DRAM samples it with various VREF(DQ) values (set via MR14 for byte 0, MR15 for byte 1 in LPDDR5), and feeds back fail patterns. The PHY finds the optimal MR14/MR15 value that maximises the read eye height.

Host-side VREF for DQ (write VREF): The PHY's own internal VREF for its DQ receivers (used when reading back DQ during DRAM training). This is adjusted in PHY registers, not DRAM mode registers.

VREF(CA): Covered under CA training above (MR12).

A key subtlety: host-side and DRAM-side VREF must be optimized independently because they're at opposite ends of the channel with different impedances and noise coupling.

How Training Relates to Signal Integrity at High Frequencies

At 6400 Mbps (LPDDR5X), the channel attenuation, ISI (intersymbol interference), crosstalk between adjacent lines, and pattern-dependent jitter all degrade the signal eye. Training finds the operating point that maximises eye margins against these degradations. The trained VREF values and delay-line settings effectively compensate for:

  • PCB trace length mismatch (write leveling, CA training)
  • DRAM output timing variation (read gate training, per-bit deskew)
  • Driver impedance variation (ZQ calibration)
  • Receiver threshold variation (VREF training)

Point-to-point topology (used by LPDDR5, including on RK3588) avoids stub reflections that plague fly-by DDR4/DDR5 topologies, but each device must still be individually calibrated because there is no stub to act as a "shared reference."

Why Training Must Be Redone Every Boot

  1. CMOS temperature dependence: The delay lines inside the PHY use CMOS inverter chains. Gate delay is proportional to 1/f, where f depends on carrier mobility — this decreases with temperature. A trained delay setting at 25°C is wrong at 75°C.
  2. Supply voltage: CMOS delay is inversely proportional to VDD. A 3% voltage sag shifts delay lines noticeably at GHz rates.
  3. On-die termination (ODT): CMOS pull-up/pull-down termination resistors drift ±20% over PVT. ZQ recalibration compensates, but requires re-running training.
  4. DRAM internal state: The DRAM's VREF and mode register values (MR12, MR14, MR15) are volatile — they reset on power-down, so the trained values must be reprogrammed each boot.
  5. No non-volatile storage in PHY: The PHY's delay-line registers are SRAM-backed, lost on power-off.

Note: DDR5 (desktop) has a "Memory Context Restore" (MCR) feature that saves training results to SPD EEPROM, allowing faster boot. LPDDR5 does not have an equivalent mechanism in the JEDEC spec, so full training runs every boot. Some platforms (DDR5 desktop) attempt to cache and restore results, but this is optional and often disabled due to instability.

Part 2: Rockchip RK3588 DDR Init — Known Issues, Patches, Community Work

Architecture of the RK3588 DDR Stack

The RK3588 uses a four-channel 64-bit memory interface (4× 16-bit channels, each with its own DDR controller instance). The boot chain:

BootROM (on-chip ROM) → DDR blob (TPL, closed-source) → SPL → U-Boot proper → Linux

The DDR blob is the Tertiary Program Loader (TPL) — a standalone Rockchip-proprietary binary. It:

  • Initialises the Synopsys DWC LPDDR5/4x PHY IP
  • Runs the full training sequence for the programmed frequency + 5 alternative frequency set points (FSPs)
  • Passes the trained frequency table to the kernel via the DMC (Dynamic Memory Controller) subsystem
  • Sets boot_fsp (the active frequency on boot, default FSP0)

After boot, BL31 (ARM Trusted Firmware EL3 runtime) handles:

  • Periodic background re-training (to compensate runtime temperature drift)
  • DDR DVFS (Dynamic Voltage/Frequency Scaling) — switching between trained FSPs on demand
  • The DDR debug interface (accessible from Linux userspace as of BL31 v1.51)

DDR Blob Versioning and the 2736 MHz Drop

Key version history (from rkbin/doc/release/RK3588_EN.md and Armbian/community tracking):

Version Date LP4 MHz LP5 MHz Key Changes
v1.09–v1.12 2022–2023 2112 2736 Initial release; v1.12 adds training result printing and MR value output for debug
v1.15 late 2023 2112 2736 Last version with LP5-2736 support; PHY skew > DLL lock value fix; data training improvements
v1.16 2024-02-04 2112 2400 LP5 frequency changed from 2736 → 2400 MHz; CS0/CS1 asymmetric capacity support; DERATEINT MR4 read interval adjustments
v1.17 2024-04-12 2112 2400 Fixed PLL ID setting bug when boot_fsp ≠ 0 (caused hangs during DDR init with non-default FSP)
v1.18 2024-09-05 2112 2400 tTOT config change for DRAM compatibility; DVFS and periodic training enabled; mixed x16/x8 die support; fixed single-rank LPDDR5 derate hang; requires BL31 ≥ v1.47
v1.19 2025-04-21 varies varies Added RK3582; introduced LP4-2112/LP5-2400 eyescan variant (_eyescan_v1.19.bin)

Why 2736 MHz was dropped in v1.16: Rockchip dropped the 2736 MHz LPDDR5 configuration (LPDDR5-5472 MT/s) in favour of 2400 MHz (LPDDR5-4800 MT/s) specifically to improve stability. The v1.16 changelog states "Altered LPDDR5 frequency settings for enhanced reliability" and the Armbian community confirmed the change when updating from rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.15.bin to rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin. The 2736 MHz operation was apparently marginal on many production boards — training would pass but the running system was susceptible to data errors or hangs, particularly with single-rank LPDDR5 configurations. The Thomas Kaiser investigation of the Radxa Rock 5 ITX noted that "bandwidth did not improve and latency got worse" with LPDDR5 vs LPDDR4X, and Rockchip/Radxa confirmed this was partly because the LPDDR5 frequency was intentionally kept conservative for stability.

The OpenBSD u-boot port update in April 2024 documents the explicit filename change from v1.12 (lp5_2736) to v1.16 (lp5_2400).

The tTOT and Derate Issues (v1.18)

Two distinct bugs addressed in v1.18:

  1. tTOT configuration: tTOT (total oscillator time) is a timing parameter controlling burst lengths and turnaround timing in the DDR controller. The misconfiguration caused incompatibility with certain DRAM die combinations (particularly mixed x16/x8 packaging). This manifested as instability or data errors with specific LPDDR5 modules.

  2. Single-rank LPDDR5 derate hang: LPDDR5 "derating" is a mandatory JEDEC feature where refresh intervals are shortened at elevated temperatures (read from the DRAM's internal temperature sensor via MR4). When derating was enabled on a single-rank LPDDR5 configuration, the DDR controller's DERATEINT.mr4_read_interval was misconfigured, causing the kernel to hang when the DMC attempted a frequency switch (DVFS operation). v1.18 fixes both the DERATEINT setting and the underlying derate logic for single-rank.

The v1.18 release note explicitly states BL31 must be v1.47 or higher — without the updated BL31, the derate fix in the DDR blob is insufficient because BL31 also participates in derate-related power management.

Known Boot Stability Issues

Community-reported pattern 1 — Old blob + 2112 MHz LPDDR4X hang: Armbian forum documented that systems running DDR at 2112 MHz with old rkbin files (pre-v1.12) would hang intermittently (forum thread: "update rkbin files of rk3588 to avoid system hangs when ddr freq is 2112MHz"). Fix: update blob.

Community-reported pattern 2 — Mismatched SPL and DDR blob: If the SPI Flash contains one DDR blob version and the SD card contains a different SPL, training can pass but produce an unstable system ("SPL and DDR blobs will not match, causing problems in training the RAM which can lead to an unstable system"). This is a documented cause of random crashes.

Community-reported pattern 3 — boot_fsp bug (v1.17 fix): Setting boot_fsp to a non-zero value (to boot at a lower DDR frequency for power saving) triggered a PLL ID misconfiguration that could hang during DDR initialisation. Fixed in v1.17.

Rock 5 ITX cold boot restarts: There is an active Gentoo Forums thread (January 2026) specifically about "Radxa Rock 5 ITX (RK3588) restarts during boot" — the exact content was inaccessible via WebFetch but this matches the class of issues where DDR training transiently fails on cold starts and the SoC's watchdog resets the board.

ArmSoM low-temperature testing: ArmSoM ran -20°C cold-soak tests (4 hours, 2000 power cycles) and reported no anomalies — suggesting the blob handles cold-start training correctly within the validated range, though their testing used current blob versions.

The eyescan Blob Variant

The file rk3588_ddr_lp4_2112MHz_lp5_2400MHz_eyescan_v1.19.bin is a special debug build of the DDR blob released alongside the standard blob starting with v1.19. It includes additional instrumentation to perform 2D eye scanning (voltage-timing sweep) and output the eye diagram data — the same data that would normally be used internally during 2D training, but now exposed for PCB/signal integrity engineers.

What it does:

  • Runs the standard training sequence
  • Additionally sweeps VREF and timing delay combinations across a grid, recording pass/fail for each
  • Outputs the 2D eye data (can be visualised as a voltage vs timing heatmap)
  • The ddrbin_tool exposes three eyescan modes: 2D eye scanning (both VREF and skew), write vref scan (applies results to write), read vref scan (applies results to read)

Intended use: PCB validation during board bring-up. Engineers flash the eyescan blob, boot the board, capture UART output with the 2D eye data, and use it to verify signal integrity and diagnose trace routing issues. It is NOT intended for production use — it runs slower (exhaustive sweep) and outputs debug data.

How to activate: Set the eye scan mode bits via ddrbin_tool (the ddrbin_param.txt configuration file controls this), flash the eyescan blob variant, and boot.

The rkddr Tool (hbiyik)

GitHub: https://github.com/hbiyik/rkddr

rkddr is a terminal UI (TUI) binary editor for Rockchip DDR blobs that runs on the RK3588 board itself. It automates the process of modifying the DDR blob's embedded configuration table and writing it back to the boot block device.

Supported targets: RK35xx series only.

How it works:

  • Reads the IDBlock (combined TPL+SPL boot image) from the boot block device (eMMC, SD, SPI), or a raw DDR blob file
  • Parses the blob's internal parameter table (the same table that Rockchip's ddrbin_tool.py manipulates)
  • Presents a TUI with editable fields
  • Writes the modified blob back with automatic backup to ~/.rkddr/

Key parameter: LP5 frequency — Setting [lp5] → first line → 3200 configures the DDR blob to train and run LPDDR5 at 3200 MHz (6400 MT/s, the JEDEC maximum). The rkddr author notes "all DDR5 rk3588 boards are tuned with under-frequency" by default, meaning Rockchip/OEMs ship conservative settings.

Kernel side requirement: After flashing the overclocked blob, a device tree overlay is also needed. The rockchip-rk3588-dmc-oc-3500mhz overlay updates the DMC driver's frequency table to include the new higher frequency steps.

Training implication: When the blob is modified to a new frequency, it trains that new frequency + 5 alternatives on next boot. The blob's internal FSP table stores timing parameters for each trained frequency; the kernel DMC driver then uses these frequencies for runtime DVFS.

Risk: If the new frequency fails training (training returns errors), the board can freeze at boot. Recovery requires maskrom mode to reflash the IDBlock from backup.

SkatterBencher Overclocking (2025)

SkatterBencher documented LPDDR5-6400 (3200 MHz) on Orange Pi 5 Max (RK3588) in August 2025 (article #89), and extreme overclock to 3454 MHz on RK3588 in September 2025 (article #91) using liquid nitrogen. The 3200 MHz stable overclock uses:

  1. rkddr to set LP5 frequency to 3200 in the blob
  2. rockchip-rk3588-dmc-oc-3500mhz DT overlay
  3. Verified the LPDDR5 modules' rated speed matches target (checking JEDEC MR8 speed grade)

The 3454 MHz extreme was achieved at cryogenic temperatures only.

Reverse Engineering Efforts

Status: minimal/none for the DDR blob itself.

Rockchip's license explicitly prohibits reverse engineering the DDR blob. There is no public documented RE effort for the DDR training code.

What exists:

  • DualTachyon/rk3588-tools (GitHub): Deals with bootloader packaging and signing, not DDR training internals. It handles the blob as an opaque binary and uses --471/--472 parameters to identify binary segments.
  • open-rk3588 GitHub organisation: Hosts open-source U-Boot, kernel, TF-A, OP-TEE for RK3588 but does not include open-source DDR init — the DDR blob remains the critical missing piece.
  • Collabora's 2024 blog ("Almost a fully open-source boot chain for RK3588"): The only remaining closed-source component is the DDR init blob. Collabora's work made TF-A/BL31 open source (upstream TF-A), but DDR training was explicitly excluded. U-Boot documentation states "instructions will be updated in the future once U-Boot gains support for open-source DRAM initialization in TPL" — but as of early 2026, no such open-source implementation exists or is publicly in progress.
  • Tomeu Vizoso's NPU reverse engineering (2024) successfully produced an open-source NPU driver for RK3588, setting a precedent — but no similar effort has been announced for DDR training.
  • Rockchip has publicly stated "there is no plan to open source the DDR init binary for RK35xx SoCs."

BL31 DDR debug interface (v1.51): Not reverse engineering, but worth noting — BL31 v1.51 added a DDR debug interface accessible from Linux userspace, enabling runtime memory diagnostics and tuning. This allows reading training results and live parameters without needing to RE the blob.

ddrbin_tool (Rockchip-provided): Rockchip does provide a Python-based ddrbin_tool.py (source available) that can read and write the parameter table embedded in the blob. This gives community members legitimate access to ~30 configurable parameters without RE. The tool's user guide documents the full parameter space (frequencies, VREF, ODT, driver strength, periodic training interval, FSP selection, spread spectrum, DQ remapping, eye scan mode, etc.).

Community Forum Threads and Patches

Armbian:

  • Forum thread: "update rkbin files of rk3588 to avoid system hangs when ddr freq is 2112MHz" — documents LPDDR4X at 2112 MHz hangs with old blobs, fixed by updating rkbin.
  • PR armbian/build#6810: "rk3588: bump default blobs (DDR:1.16, BL31:1.45)" — the PR that standardised the community on the 2400 MHz LP5 blob.
  • PR armbian/build#7872: Updated to DDR v1.18 / BL31 v1.48; maintainer comment: "I hope there is not regression for other models" — showing the cautious approach to blob updates.
  • PR armbian/rkbin#25 and armbian/rkbin#34: Armbian maintains its own rkbin fork with patch notes.

Radxa:

  • "ROCK 5B Debug Party Invitation" (forum.radxa.com): Long thread about Rock 5B stability debugging; DDR blob/BL31 version mismatch identified as a root cause in multiple cases.
  • Joshua-Riek ubuntu-rockchip PR#853: "radxa-rock5: update bl31 and ddr blob to improve stability."
  • Community note: when SPL in SPI flash and DDR blob on boot media don't match, training produces an unstable system.

Gentoo: Thread "Radxa Rock 5 ITX (RK3588) restarts during boot" (January 2026) — specific to the Rock 5 ITX+, matching the user's hardware.

XDA: Thread "Firmware and Modifications for Rockchip RK35xx" documents rkddr usage, blob modification, and community overclock experiences.

Kernel mailing list: Jonas Karlman (kwiboo) submitted patches in March 2023 "rockchip: Use an external TPL binary on RK3588" (patchwork.ozlabs.org project uboot, patch 20230321214301) enabling mainline U-Boot to use the Rockchip DDR blob as an external TPL, since U-Boot has no internal DDR init for RK3588. This is now the standard approach in upstream U-Boot.

Part 3: Synopsys DWC LPDDR5 PHY on RK3588

What PHY IP Does RK3588 Use?

The RK3588 TRM (Part 2, Stanford hosted) references the DDR memory controller and PHY. The Synopsys product page confirms the DWC_LPDDR54_PHY (DesignWare LPDDR5/4/4X PHY) as the IP family targeting SoCs that support LPDDR5/4/4X. Independently, the Synopsys dwc_ac_lpddr54_controller and DWC_LPDDR54_PHY appear in chip estimation databases matching RK3588's feature set. The Synopsys product naming for this IP is DWC_LPDDR54_PHY (or its successor DWC_LPDDR5X54X_PHY for LPDDR5X). Rockchip has licensed Synopsys DDR IP for previous RK3xxx generations as well, making this a well-established relationship. Confirmation that Rockchip specifically uses Synopsys DWC IP for RK3588 comes from multiple indirect sources (TRM register naming conventions, the Synopsys LPDDR54 controller/PHY product matching the feature set, community reverse engineering observations of blob register writes), but Rockchip does not officially publish the IP vendor name in public documentation.

Synopsys DWC PHY Architecture and Training Sequence

The Synopsys DWC LPDDR5/4/4X PHY uses a PHY Utility Block (PUB) architecture. Key components:

  • MASTER block: Top-level PHY control, DLL (Delay-Locked Loop), PLL
  • ANIB (Address/Command Interface Block): Handles CA signals
  • DBYTE (Data Byte block): One per byte lane; contains DQ/DQS I/O, per-bit delay lines (BDL — Bit Delay Line), byte-level delay lines (LCDL — Local Clock/DQS Delay Line), DQS gate logic
  • DRTUB (DFI Real-Time Update Block): Handles DFI training interface to the memory controller
  • PIR (PHY Initialization Register): Writing specific bits triggers specific training steps; the firmware orchestrates the sequence by setting PIR bits and monitoring the PGSR (PHY General Status Register)

Training sequence for LPDDR5 (Synopsys DWC firmware):

The firmware is loaded into the PUB's embedded microcontroller (a small proprietary core, not ARM) at boot time by the Rockchip DDR blob. The firmware then executes:

  1. PHY initialisation (PLL lock, DLL calibration)
  2. ZQ calibration
  3. DRAM initialisation (MRS programming to set LPDDR5 operating modes)
  4. CBT (Command Bus Training) — Mode 1, then Mode 2 if VREF(CA) training desired
  5. WCK2CK leveling
  6. Write leveling
  7. Read gate training (RDQS gate)
  8. WCK-DQ 1D training (write DQ deskew)
  9. Read DQ 1D training (per-bit deskew + centering)
  10. Write DQ 1D training
  11. Read-Write 2D eye training (voltage + timing sweep)
  12. Write VREF training (DQ VREF for host side)
  13. Read VREF training (VREF(DQ) in DRAM, MR14/MR15)
  14. RDQS Toggle Mode / Enhanced RDQS training

The 1D stages find timing centres; the 2D stages then refine by adding the voltage dimension. Synopsys's DDR5/4 PHY Training Firmware Application Note (Document Version I now have comprehensive research across all three areas. Let me compile the full technical report.

DDR PHY Training, RK3588 DDR Init, and Synopsys DWC LPDDR5 PHY: Deep Technical Report

Part 1: LPDDR5 DDR PHY Training — The Complete Technical Picture

Why DDR Training Exists At All

At the data rates LPDDR5 operates at (up to 6400 Mbps, or 3200 MHz clock), a signal takes a measurable and variable amount of time to travel from the memory controller PHY to each DRAM chip. PCB trace lengths are never perfectly identical. Semiconductor delay cells (the inverter chains and delay-locked loop tap elements inside the PHY) are never precisely at their nominal value — their resistance and capacitance shift with temperature and supply voltage. On-die termination (ODT) resistors are nominally 240 Ohm but are tunable precisely because CMOS devices vary with process, voltage, and temperature (PVT).

At low frequencies (DDR2 era, ~400 MHz), these variations were small relative to a bit period and could be tolerated with static margin. At LPDDR5 6400 Mbps, the entire bit period is ~312 ps, and a 100 ps mismatch represents 32% of the unit interval — a catastrophic error. Training is the process of sweeping delay parameters, measuring pass/fail on a known pattern, and locking in the optimal operating point for that specific chip, board, temperature, and voltage at the moment of boot.

Training results are not stored in non-volatile memory between power cycles for fundamental physics reasons: even if you stored the delay tap counts from the last boot, the actual delay per tap changes with temperature and voltage. A system that trained at 70C at 1.1V will have completely wrong delay settings when booted at 20C at 1.05V. All DDR training must be redone from scratch on every cold boot, and re-applied after every suspend/resume cycle (hence BL31's responsibility to restore DVFS/periodic training state after wake-up on RK3588).

There is also in-operation periodic retraining: the Synopsys DWC PHY Utility Block (PUB) continuously compensates delay lines against VT drift during runtime, typically every ~100 ms (configurable via the periodic training interval register in the ddrbin_tool).

The LPDDR5-Specific Clocking Architecture and Why It Complicates Training

LPDDR5 introduced a fundamentally different clocking architecture compared to LPDDR4. LPDDR4 used a single CK clock at full frequency plus DQS strobes toggled by the host. LPDDR5 separates the clocks into:

  • CK_t/CK_c: The command clock, running at up to 800 MHz (1600 MT/s). This is the clock that the command/address (CA) bus is referenced to.
  • WCK_t/WCK_c: The Write Clock, which runs at 2x or 4x the CK frequency (1600 or 3200 MHz at the DRAM package). For 6400 MT/s data rate, WCK runs at 3200 MHz. The DRAM uses WCK both to capture write data from the host and to generate the RDQS strobe and DQ output for reads.

The ratio of WCK:CK can be 2:1 or 4:1, selectable via the CKR mode register. At LPDDR5-6400 (3200 MHz WCK, 800 MHz CK), the ratio is 4:1. Decoupling WCK and CK is power-efficient but requires an explicit synchronization step before any data transfer can occur. The LPDDR5 SDRAM requires internal synchronization of these signals following a specific protocol: at least one CK cycle of WCK static, one CK of half-rate WCK activity, then full-rate WCK. This synchronization must happen each time the WCK is enabled.

This architecture necessitates training steps that do not exist in LPDDR4:

  • WCK2CK Leveling (analogous to LPDDR4 write leveling): aligns the phase of WCK at the DRAM package relative to CK. Because WCK travels point-to-point from PHY to DRAM (unlike LPDDR4's DQS which uses a fly-by topology), this is a per-channel operation. The PHY sweeps the WCK output delay until the DRAM sees the correct CK-to-WCK relationship.
  • WCK DCA (Duty Cycle Adjustment) training: LPDDR5 has a separate WCK DCA training to correct for differential duty cycle distortion on the WCK lines.

Training Step 1: Write Leveling (WCK2CK Leveling for LPDDR5)

In LPDDR4 and DDR4, write leveling compensates for the fly-by clock topology where the CK daisy-chains through all DRAM chips but DQS is point-to-point. For LPDDR5, WCK2CK leveling serves the analogous purpose.

Mechanism: the DRAM is placed in write leveling mode (via MR register). The host controller then asserts WCK and varies its delay using the PHY's output delay elements (typically a DLL-based delay line with fine-grained taps). At each delay setting, the DRAM samples the CK signal and returns a 0 or 1 on DQ[0]. The controller finds the transition from 0 to 1, which marks where the WCK edge aligns with the CK edge. This training is per-DRAM-chip, per-channel, since each chip on the bus experiences a different propagation delay.

The result is a set of WCK output delay register values that bring WCK into proper phase alignment with CK at the DRAM input. Without this, the DRAM cannot correctly synchronize the 4:1 CK:WCK relationship, and all write data capture fails.

Training Step 2: Gate Training (Read DQS Gate, RDQS Toggle Training)

During reads, the LPDDR5 DRAM generates RDQS (Read Data Strobe) using WCK as its clock source. RDQS travels from DRAM to PHY. The PHY must "open the gate" — enable its input capture latch — at precisely the right time to catch the incoming RDQS pulse. Open too early and you capture noise before RDQS arrives; open too late and you miss the valid data window.

Training mechanism: the PHY sweeps the read gate delay (using a delay line controlling when the DQS gate enable is asserted). Without using any DQ data, the PHY samples RDQS at each delay setting. A transition from "RDQS not present" to "RDQS detected" identifies the RDQS arrival window. The gate delay is set to the center of this window.

For LPDDR5, JESD209-5 defines additional variants:

  • RDQS Toggle Mode: the DRAM continuously toggles RDQS without data, allowing gate training
  • Enhanced RDQS Toggle Mode: uses a pattern-based approach for more precise gate centering

This step is purely within the PHY (the PUB's built-in read DQS gate training unit) and does not require the DRAM to be in a special training mode beyond enabling the toggle.

Training Step 3: Read DQ Training — Per-Bit Deskew and Eye Centering

After gate training, the PHY knows when to open the read window. But within a 16-bit data byte group, each individual DQ bit arrives at slightly different times due to trace length variation (even with matched routing, tolerances are +/- a few mils) and package-level differences inside the DRAM die.

Per-bit read deskew: The PHY sweeps an individual delay element on each DQ line independently (each bit has its own delay-line element in the PHY data slice). For each DQ bit, the delay is swept while the controller sends a known pattern and checks pass/fail. The DRAM is placed in read DBI / read preamble mode. For each delay value, the PHY reads and compares the received bit to the expected pattern. The leftmost passing delay and rightmost passing delay define the data eye for that bit. The per-bit delay is set to the center of that eye. This procedure is performed separately for all bits.

Read eye centering: After per-bit deskew equalizes all DQ bits relative to each other (making them arrive simultaneously from the PHY's perspective), the DQS strobe must be centered within the equalized data eye. The PHY then sweeps the RDQS sampling point (or equivalently shifts all DQ delays together) to find the center of the combined eye and locks in that position.

The Synopsys PUB calls these operations using the PIR register bits. The PHY training firmware executes read 1D training (timing sweep only) as a baseline, and optionally 2D training (simultaneous sweep of both timing and voltage/VREF) for a more accurate eye measurement.

Training Step 4: Write DQ Training — Per-Bit Deskew and Eye Centering

The write path has the same problem in reverse: the host PHY drives DQ bits from its output delay elements, but interconnect variation means each bit arrives at the DRAM at slightly different times relative to WCK.

Per-bit write deskew (WCK2DQ training in LPDDR5): the DRAM is placed in write DQ training mode. The controller sends a known PRBS pattern with varying delays on individual DQ lines. The DRAM samples with WCK, returns pass/fail on the DQ lines (in LPDDR5 via the DQ loopback or mode-register-based feedback mechanism). Per-bit write delays are adjusted to center each DQ bit in the write eye.

Write eye centering: after per-bit deskew, WCK is swept relative to the DQ group to center the strobe within the equalized write eye.

Training Step 5: VREF Training

At LPDDR5 data rates, receiver sensitivity (the ability of a CMOS input buffer to correctly distinguish a logic 1 from a logic 0) depends critically on the threshold voltage — the VREF. Due to impedance mismatches, ISI (inter-symbol interference from channel loss and reflections), and supply noise, the optimal VREF is not simply Vdd/2 and varies per-channel, per-die, and per-direction.

There are two distinct VREF training loops:

Host-side VREF (PHY side): The PHY has internal VREF DACs for its DQ input comparators. During read VREF training, the controller sweeps the PHY internal VREF while running a known read pattern. For each VREF setting, the read eye width is measured. The VREF is set to maximize eye opening. This compensates for the AC coupling of the channel to the PHY receiver.

DRAM-side VREF: Controlled via LPDDR5 Mode Register MR14 (for DQ VREF) and MR15 (upper byte). The controller writes different VREF values to MR14/15 while performing write-read-compare cycles. This is a 2D sweep: at each VREF step, the write timing is also varied to build a 2D eye map (VREF on one axis, timing on the other). The optimal VREF minimizes BER across the widest timing window.

Note that VREF settings have both a voltage-calibration aspect (finding the right DC operating point) and a margining aspect (finding the point that maximizes the write eye area). This is exactly what the ddrbin_tool parameter "write vref scan" and "read vref scan" expose for the Rockchip DDR blob.

Training Step 6: CA (Command/Address) Training — CBT

The command/address bus in LPDDR5 runs at CK-referenced timings (1600 MT/s for the CA bus, since the CK itself runs at 800 MHz and CA is DDR). The CA bus drives the DRAM's command and address pins. At 1600 MT/s, the CA bus must also be trained for both timing alignment (centering CA edges relative to CK) and voltage reference (VREF(CA), programmed via MR12).

LPDDR5 Command Bus Training (CBT) comes in two modes defined by JEDEC JESD209-5:

CBT Mode 1: The DRAM is placed in CBT training mode. The host drives CS and CA bits which the DRAM captures on one edge of CK. The sampled CA values are returned statically on DQ pins (DQ[7:0]). The host reads these back and determines which CA delays are margined. The host sweeps the CA output delay in the PHY and finds the passing window. The CA delay is set to center of the window. No VREF adjustment is possible in Mode 1 without exiting training.

CBT Mode 2: Requires the DMI pin to participate. The DRAM samples DQ[6:0] on the rising edge of DMI[0] to update MR12 (VREF(CA)) values — all while remaining in CBT training mode, without requiring a mode-exit/re-entry sequence. This allows simultaneous timing-and-VREF sweep in a single training pass. VREF(CA) is set via the MR12.OP[6:0] field, and the host uses the DMI pin to communicate VREF updates to the DRAM without disrupting the CA training loop. The result is a 2D optimization of CA timing and VREF(CA) simultaneously.

Signal Integrity at High Frequencies: Why Training is Non-Negotiable

At 6400 Mbps:

  • Bit period: ~312 ps
  • At LPDDR5 data rates, even 5 ps of uncompensated skew represents 1.6% of UI
  • PCB trace length matching requirement: +/- 25 mil (which introduces ~0.2 ps of delay difference at typical FR4 propagation velocity of ~6 in/ns)
  • Package internal trace variations: 10-50 ps, not controllable by PCB designer
  • Silicon process variation in delay cells: ±20% at ±10% voltage, ±10% temperature range

For the RK3588's quad-channel LPDDR5 implementation (4x 16-bit channels forming a 64-bit bus, with LPDDR5 chips connected point-to-point), the design guide specifies:

  • Single-ended DQ/DM impedance: 40 Ohm ± 10%
  • Differential DQS/CLK impedance: 80 Ohm ± 10%
  • All DQ and CA signals use point-to-point topology (not fly-by)
  • ODT must be dynamically adjusted per frequency

The point-to-point topology of LPDDR5 (vs. the fly-by topology of DDR4 DIMMs) simplifies write leveling requirements but does not eliminate per-bit deskew needs from package-internal routing variations.

Part 2: RK3588 DDR Init — Community Issues, Tools, and Specifics

The DDR Blob Architecture on RK3588

The RK3588 boot chain: BootROM → Idblock (DDR TPL + SPL) → U-Boot proper → BL31 (TF-A) → Linux

The DDR blob serves as the Tertiary Program Loader (TPL), executing before even the SPL. It is the first code to run from SRAM, and its job is to bring LPDDR5/LPDDR4X online so that SPL and U-Boot can load into DRAM. The blob is a binary proprietary firmware distributed in the Rockchip rkbin repository. Rockchip explicitly forbids reverse engineering in their license.

The blob trains the primary boot frequency plus 5 additional frequencies (the FSPs — Frequency Set Points). These trained frequencies and their timing parameters are passed to the kernel's DMC (Dynamic Memory Controller) governor via the DFI (DDR Frequency Interface), enabling DVFS for DDR. The kernel's DMC driver gets two frequency sources: what the DDR blob provides from training, and what is specified in the DTS. The kernel uses whichever frequency the DTS specifies that is less than or equal to a blob-trained frequency.

The DDR blob also contains embedded firmware for the Synopsys PHY Utility Block — the training algorithm firmware that programs the PHY's training sequencer.

Known Issues and Bug History

The 2736 MHz to 2400 MHz Downgrade (v1.16, February 2024)

This is the most significant community-facing change in the DDR blob history. Before v1.16, the production DDR blob was: rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.15.bin

Starting with v1.16 (2024-02-04), the standard production blob became: rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin

The v1.16 release notes state: "Altered LPDDR5 frequency settings for enhanced reliability" along with:

  • Enabled CS0/CS1 asymmetrical capacity configurations
  • Adjusted DERATEINT MR4 read timing

The 2736 MHz clock corresponds to LPDDR5-5472 MT/s (5472 = 2736 × 2). The TRM nominally specifies LPDDR5-5500 as the top supported speed, making 2736 MHz exactly the rated maximum. The decision to drop to 2400 MHz (LPDDR5-4800) was a deliberate stability tradeoff: at 2736 MHz the training margins were too narrow for robust operation across the full PVT range of all production DRAM chips that various board vendors were using. Different DRAM suppliers (SK Hynix, Samsung, Micron) have varying timing characteristics, and a frequency that trains correctly on one chip batch may fail intermittently on another.

The DERATEINT adjustment is related to the LPDDR5 derating feature: LPDDR5 specifies that timing parameters (tRCD, tRP, tRC, tRAS) must be derated (extended) when the DRAM junction temperature exceeds 85°C. The DRAM reports its temperature via MR4. The DERATEINT register controls how frequently the controller reads MR4. Incorrect MR4 read timing caused incorrect derating behavior, which in some conditions produced training instability or post-training memory errors.

Single-Rank LPDDR5 Derate Bug (fixed in v1.18)

v1.18 (2024-09-05) fixed: "Fixed derate issue with single-rank LPDDR5" and "System might hang in kernel when switching frequency for LPDDR5 of one rank".

This was a separate bug from the MR4 timing issue. Single-rank LPDDR5 configurations (which are common on boards with smaller memory sizes) had an incorrect derate calculation path. When the DMC tried to switch DVFS frequencies at runtime (a normal DVFS operation), the derate timing computations using MR4 data were wrong for single-rank configs, causing the controller to issue an illegal timing to the DRAM. The DRAM would not respond, and the kernel would hang waiting for the controller to complete the frequency switch. This required v1.18 DDR blob and v1.47 BL31 (BL31 coordinates the DVFS frequency switch with the kernel via PSCI).

System Hangs at 2112 MHz LP4 (Armbian thread, 2023)

An Armbian build PR titled "update rkbin files of rk3588 to avoid system hangs when ddr freq is 2112MHz" documented that certain early blob versions caused hangs specifically at the highest LPDDR4X operating frequency (2112 MHz). The root cause was incorrect timing parameter calculation for the high-frequency LPDDR4X operating point. Updating from an early blob (v1.08 or earlier) to v1.09+ resolved this.

boot_fsp != 0 Bug (fixed in v1.17)

v1.17 (2024-04-12) fixed: "Corrected PLL ID configuration when boot_fsp parameter differs from default". The FSP (Frequency Set Point) selection parameter boot_fsp allows the blob to boot at a frequency other than FSP0 (the lowest). Setting boot_fsp=1,2,3 to boot directly at a higher frequency caused incorrect PLL ID selection during initialization, leading to either boot failure or unstable operation. This bug affected users trying to use the ddrbin_tool to change the boot FSP.

tTOT Modification (v1.18)

tTOT is the Turn-Off Time parameter — a timing parameter governing when termination is disabled during idle periods. Incorrect tTOT values can cause signal integrity issues when the bus transitions between active and idle states. The v1.18 release notes state: "Modified tTOT configuration to improve DRAM compatibility" — this targeted compatibility with specific DRAM vendors whose chips have stricter tTOT requirements.

The Eyescan Blob Variant

Rockchip ships a separate DDR blob variant with "eyescan" in the filename: rk3588_ddr_lp4_2112MHz_lp5_2400MHz_eyescan_v1.19.bin

This is a debug and validation firmware variant, not a production variant. It enables 2D eye scan data collection via the Synopsys PHY's diagnostic capabilities:

The Rockchip ddrbin_tool exposes three eye scan modes:

  1. 2D eye scan: sweeps both VREF (voltage) and timing (delay taps) independently, generating a 2D map of pass/fail regions. The resulting eye diagram shows the "eye opening" — the region in the voltage-timing space where the memory reliably operates without errors.
  2. Write VREF scan: applies 2D scan results to write VREF optimization
  3. Read VREF scan: applies 2D scan results to read VREF optimization

The eyescan blob instruments the PHY to output these eye map results, typically over UART, during boot. This data allows board engineers to:

  • Validate that DDR routing on a PCB design has adequate margins
  • Identify manufacturing defects (solder bridging, trace damage) that narrow the eye
  • Determine optimal VREF settings for mass production
  • Characterize DRAM vendor/lot differences

The eyescan blob is used by Rockchip reference design teams and SBC vendors (Radxa, Orange Pi, etc.) during hardware bring-up, not by end users.

The rkddr Tool (hbiyik)

Repository: github.com/hbiyik/rkddr

rkddr is a TUI-based DDR blob editor for RK35xx boards (RK3566, RK3568, RK3588 series). It addresses the usability gap in Rockchip's official ddrbin_tool.py: while ddrbin_tool requires Python, a parameters text file, and manual flashing, rkddr automates the full workflow.

How it works:

  • Detects the DDR blob on block device, idblock, or raw file
  • Presents a TUI showing editable parameters
  • On save, automatically backs up the original to ~/.rkddr/ and writes the modified blob back to the device (no maskrom mode needed for routine changes)
  • The kernel then reads the trained frequencies from the modified blob at next boot

Primary use case on RK3588: overclocking LPDDR5 beyond the production 2400 MHz setting to approach 3200 MHz (6400 MT/s). The key insight is that the DDR blob trains all configured FSP frequencies at boot — if you set FSP0=3200 MHz, the blob will attempt to train at 3200 MHz. If training succeeds (DRAM supports it, routing margins are adequate), the kernel receives 3200 MHz as an available frequency.

The rkddr README notes: "all DDR5 rk3588 boards are tuned with under-frequency" — a direct acknowledgment that production boards are running LPDDR5 below its rated maximum for stability reasons.

Required companion: a device tree overlay (rockchip-rk3588-dmc-oc-3500mhz) that adds the overclocked frequency and corresponding voltage to the DMC OPP table in the DTS. The kernel's DMC governor needs this DTS entry to know what voltage to apply when switching to the higher DDR frequency.

Overclocking results reported by community (from SkatterBencher #89, #91 and sbcwiki):

  • Orange Pi 5 Max: stable at 2650 MHz (5300 MT/s) at stock voltage
  • RK3588 extreme OC (SkatterBencher #91): 3454 MHz (6908 MT/s) achieved with LN2 cooling
  • Standard room temperature OC ceiling: approximately 2800-3200 MHz depending on DRAM lot, board quality, and cooling

Risk: if training fails at the configured frequency, the board freezes in early boot. Recovery requires maskrom mode to flash a stock idblock. There is no CMOS-style jumper reset.

Rockchip ddrbin_tool (Official)

Usage: python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"

Configurable parameters for RK3588 include:

  • LP5 frequency range: 400 MHz – 2750 MHz (per documentation, though >2400 MHz is not in production blobs)
  • LP4/LP4x frequency range: 306.5 MHz – 2133 MHz
  • boot_fsp: 0–3, selects which FSP to boot at
  • Eye scan modes: 2D eye scan, write VREF scan, read VREF scan
  • Periodic training interval: 0 = disabled, any other value = interval in 100 ms units
  • TRFC mode: default / next density / max / min
  • VREF settings: PHY-side and DRAM-side VREF for both ODT-on and ODT-off states
  • Driver strength: DQ and CA driver impedance in Ohm
  • ODT values: and frequency threshold below which ODT is disabled
  • Slew rate: 0x0–0x1f range
  • Spread spectrum: center/down/up spread, amplitude control (for EMI reduction)
  • DQ remapping: byte and individual bit remapping within the PHY
  • SR/PD idle: self-refresh and power-down delay timers
  • 2T timing mode: enable/disable
  • first_init_dram_type: specifies DRAM type to try first, accelerating training convergence

DDR Training Debug: v1.12+ MR Printing, BL31 Debug Interface

Starting with DDR blob v1.12, Rockchip added the ability to print training results and Mode Register values over UART during boot. This allows engineers to see the actual trained delay tap values, the per-bit deskew results, and the DRAM's MR4 temperature reading — all without needing the separate eyescan blob.

BL31 v1.51 added a runtime DDR debug interface accessible from Linux. This allows Linux userspace (or kernel drivers) to query and potentially modify DDR controller and PHY state at runtime — a significant diagnostic capability. Combined with the DFI (DDR Frequency Interface) driver at drivers/devfreq/event/rockchip-dfi.c, this enables runtime observation of DDR utilization and frequency state.

Community Forum Activity

Armbian forums (forum.armbian.com/topic/28964, topic/6810): PR #6810 bumped the Armbian default blobs from DDR v1.08→v1.16 and BL31 v1.28→v1.45, removing board-specific blob overrides for boards that had been pinned to older versions.

Radxa community (forum.radxa.com/t/rock-5b-debug-party-invitation/10483): The Rock 5B Debug Party was an extended community debugging effort. Users reported that mismatched DDR and BL31 blob versions (e.g., SPL from SPI flash vs. DDR blob from SD card) caused training instability and random crashes. The solution is always to ensure DDR blob + BL31 + SPL are from the same compatible set — specifically, DDR v1.18+ requires BL31 v1.47+.

Gentoo forums (forums.gentoo.org, January 2026): Recent thread about Radxa Rock 5 ITX (RK3588) restarting during boot — directly relevant to Radxa Rock 5 ITX+ users. The typical resolution involves ensuring the DDR blob and BL31 are current and matched versions.

XDA forums (xdaforums.com/t/firmware-and-modifications-for-rockchip-rk35xx-rk3566-rk3588-etc.4716612): Primary community hub for RK35xx firmware modifications, including rkddr overclocking guides, ddrbin_tool usage, and stability workarounds.

OpenBSD/FreeBSD port updates (mail-archive.com/ports@openbsd.org/msg124806.html): The OpenBSD ports tree update for RK3588 u-boot (2024-04) specifically references changing rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.12.bin to rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin — the canonical documentation of the 2736→2400 MHz change in a widely-tracked upstream.

Reverse Engineering Status

Rockchip's license explicitly prohibits: "decompile, reverse-engineer, disassemble, or attempt to derive any source code from the Software."

Despite this, partial reverse engineering has occurred:

  • DualTachyon/rk3588-tools: A C toolkit for bootloader packing and signing. Confirms rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.12.bin blob structure (base address 0x00000000, --471/--472 binary segments). Does not reverse engineer the training algorithm itself.
  • open-rk3588 GitHub organization: Maintains mainline-adjacent kernel, TF-A, and OP-TEE forks. No open-source DDR init is present — this remains explicitly listed as the missing piece.
  • Collabora's open-source boot chain blog post (2024): Documents that the BL31 TF-A component was successfully opened (Rockchip cooperated), but the DDR training blob has "no plan for open sourcing" from Rockchip for the RK35xx SoCs. The instruction in U-Boot documentation explicitly states: "Instructions will be updated in the future once U-Boot gains support for open-source DRAM initialization in TPL" — acknowledging it as a goal with no current timeline.
  • NPU reverse engineering (Tomeu Vizoso): An unrelated but significant success — the RK3588 NPU was fully reverse engineered and an open-source Mesa/kernel driver was submitted. This demonstrates that Rockchip silicon reverse engineering is technically feasible, but the DDR PHY complexity (Synopsys PHY firmware is especially opaque) makes DDR init significantly harder.

LPDDR5 Bandwidth Paradox on RK3588

ThomasKaiser's Rock 5 ITX preview documented a counterintuitive result: LPDDR5 at 5472 MT/s (2736 MHz clock, the v1.15 blob frequency) showed worse latency and no bandwidth improvement compared to LPDDR4X at 4224 MT/s. Rockchip/Radxa confirmed this: LPDDR5's protocol introduces higher minimum latency than LPDDR4X as a fundamental architectural difference (more training overhead, more preamble cycles, different burst organization). This is one reason the production blob stepped down to 4800 MT/s (2400 MHz) — the bandwidth gains over LPDDR4X at 2736 MHz were marginal and the stability costs were high.

The ArmSoM low-temperature testing (−20°C, 2000 software reboots + 2000 power cycle reboots) showed no DDR training failures in controlled conditions. However, this tested the production 2400 MHz configuration. User reports of cold boot instability are more common on boards that were using the older 2736 MHz blob (v1.15 and earlier) or when component versions are mismatched.

Part 3: Synopsys DWC LPDDR5 PHY on RK3588

Which PHY Does RK3588 Use?

The RK3588 TRM Part 2 and datasheet confirm the memory controller uses a Synopsys DesignWare LPDDR5/4/4X Controller and PHY IP — specifically the DWC_lpddr54_controller and the associated DWC_LPDDR54_PHY. The Synopsys product page for dwc_lpddr54_phy (synopsys.com/dw/ipdir.php?ds=dwc_lpddr54_phy) describes the exact IP used by the RK3588.

The Synopsys product page for dwc_ac_lpddr54_controller is separately listed at ChipEstimate, confirming Synopsys IP on the RK3588. The Stanford-hosted RK3588 TRM Part 2 contains register descriptions matching the DWC LPDDR4x multiPHY Utility Block (PUB) architecture documented in the publicly available Sunxi community PUB datasheet (the LPDDR4x PUB document provides significant insight into the LPDDR5 version since they share architecture).

PHY Architecture

The Synopsys DWC LPDDR54 PHY uses a multi-rank, multi-channel architecture:

PHY Utility Block (PUB): The RTL-based PUB is the training controller. It contains:

  • Configuration registers for the entire PHY
  • A built-in training sequencer (the PIR register triggers specific training steps)
  • Periodic delay line compensation logic (continuous VT compensation)
  • ATE testing and diagnostic interface
  • The training firmware itself (embedded in the PHY as microcode)

The PUB register blocks include: ACSM (Address/Command State Machine), ANIB (Address/Command IO Block), APBONLY (APB-only registers), DBYTE (Data Byte lane), DRTUB (Debug/Training Utility Block), INTENG (Integrity Engine), and MASTER.

Data Byte slice: Each 16-bit data channel has multiple DBYTE slices (typically one per 8-bit half). Each DBYTE slice contains:

  • Individual delay line elements for each DQ bit (enabling per-bit deskew)
  • DQS delay elements
  • VREF DAC for read receiver
  • Training state machine for that slice

Address/Command IO Block (ANIB): Handles CA bus routing and WCK generation.

Synopsys LPDDR5 Training Sequence

For LPDDR5, the Synopsys firmware runs these training steps in order:

  1. ZQ calibration: Calibrates the PHY's internal ODT termination resistors against an external precision reference resistor. This is the baseline impedance calibration before any timing work.
  2. DCM/DCA training (WCK Duty Cycle and Amplitude): Corrects differential pair imbalance on WCK.
  3. WCK2CK leveling (CBT pre-requisite): Aligns WCK phase to CK.
  4. CA training (CBT): Command Bus Training — aligns CA bus timing and VREF(CA). Runs Mode 1 or Mode 2 per the configuration.
  5. Read gate training (RDQS toggle): Opens the read gate at the right time for RDQS capture.
  6. Read 1D training: Coarse timing sweep for all DQ bits — finds the read eye per byte lane.
  7. Per-bit read deskew: Fine delay adjustment per individual DQ bit.
  8. Read eye centering: Centers DQS within the deskewed read eye.
  9. Read VREF training: Sweeps PHY-internal VREF for optimal read eye.
  10. Write leveling (WCK2CK for write direction — confirms WCK delivery to DRAM for write operations).
  11. Write DQ 1D training (WCK2DQ): Coarse write timing sweep.
  12. Per-bit write deskew: Fine write delay per DQ bit.
  13. Write eye centering: Centers WCK relative to DQ group.
  14. Write VREF training (DRAM-side MR14): Sweeps DRAM VREF(DQ) for optimal write eye.
  15. 2D training (optional): Simultaneous timing + VREF sweep for both read and write to generate the full 2D eye map. This is what the eyescan blob enables in extended form.

The entire sequence runs in the PUB firmware, with the main CPU observing only via a polling-complete status register. The Synopsys firmware-based approach was chosen over hardware state machines because it allows: parallel training of multiple channels simultaneously (while main CPU is busy with other init), easy field updates to the training algorithm (firmware update without hardware respinning), and the ability to handle the complex conditional branching required for LPDDR5's multi-mode training (CBT Mode 1 vs. Mode 2 selection, etc.).

Known Synopsys DWC PHY Quirks in RK3588 Context

  • The "PHY skew value greater than DLL lock value" improvement mentioned in v1.15 release notes is a known boundary condition in the Synopsys DWC PHY: if the training algorithm selects a per-bit deskew delay tap value that exceeds the DLL's locked tap count, the delay wraps around incorrectly. The v1.15 blob added a check to clamp or adjust the result.
  • The Cortex-M0 in PD_CENTER referenced in the RK3588 datasheet's power domain description is an embedded MCU within the MSCH (Memory Scheduler) domain that assists the main DDR controller with low-power state management. It is not the DDR training engine (which is in the Synopsys PUB), but it coordinates power-gating of memory channels.
  • Periodic delay line compensation: The Synopsys PUB runs in the background during normal operation, periodically recalibrating the delay lines against VT drift. On RK3588, this is the "periodic training" feature controlled by BL31. The v1.47 BL31 bug fix "Restored status of dvfs/periodic training after system wake up" was critical: after system suspend/resume, BL31 must re-enable the PUB's periodic compensation mode because the PHY power state was modified during suspend.

Summary Table: RK3588 DDR Blob Version History (Key Milestones)

Version Date Key Changes
v1.09 2023 Base LP4/LP5 initial production blob
v1.12 2023 Added training result + MR value printing to UART
v1.15 late 2023 LP5 at 2736 MHz, fixed PHY skew > DLL lock boundary condition
v1.16 2024-02-04 Dropped LP5 to 2400 MHz for stability, fixed DERATEINT MR4 timing, added asymmetric CS support
v1.17 2024-04-12 Fixed boot_fsp != 0 PLL ID bug
v1.18 2024-09-05 Fixed single-rank LPDDR5 derate crash, tTOT fix, enabled DVFS/periodic training, mixed x16/x8 support; requires BL31 v1.47+
v1.19 2025-04-21 Added RK3582 support; eyescan variant available: rk3588_ddr_lp4_2112MHz_lp5_2400MHz_eyescan_v1.19.bin

Sources:

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