282d23fff7
FUN_0000d10c @ 0xd10c (49 insts) contains poll site 11. Semantically decoded as a PHY-side prologue for frequency-change handshake: saves current state of one PHY CTL + four secondary-table entries, waits for PHY firmware to reach state 1 (idle). Matching-decomp iteration deferred vs the clean first lift (d328) — d10c's two-base-pointer csel pattern plus parity-dependent offset chain gives GCC too much register-allocation freedom. Getting to >=90% byte-match would be an afternoon of iteration; time better spent expanding pre-UART coverage breadth. Poll-site coverage so far: d328: sites 12, 13, 14, 15 (C candidate at 89.7% size match) d10c: site 11 (reference C only, no matching iteration) Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
57 lines
2.1 KiB
ArmAsm
57 lines
2.1 KiB
ArmAsm
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func.bin: file format binary
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Disassembly of section .data:
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000000000000d10c <.data>:
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d10c: 2a0103e4 mov w4, w1
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d110: 7100043f cmp w1, #0x1
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d114: d37be886 lsl x6, x4, #5
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d118: a94c8c07 ldp x7, x3, [x0, #200]
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d11c: f8666805 ldr x5, [x0, x6]
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d120: 8b060046 add x6, x2, x6
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d124: 9a878063 csel x3, x3, x7, hi // hi = pmore
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d128: 914040a0 add x0, x5, #0x10, lsl #12
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d12c: b9418005 ldr w5, [x0, #384]
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d130: b90238c5 str w5, [x6, #568]
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d134: 529fa006 mov w6, #0xfd00 // #64768
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d138: 72bfff66 movk w6, #0xfffb, lsl #16
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d13c: b9418005 ldr w5, [x0, #384]
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d140: 0a0600a5 and w5, w5, w6
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d144: b9018005 str w5, [x0, #384]
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d148: b9401405 ldr w5, [x0, #20]
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d14c: 120008a5 and w5, w5, #0x7
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d150: 710004bf cmp w5, #0x1
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d154: 54ffffa1 b.ne 0xd148 // b.any
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d158: 12000021 and w1, w1, #0x1
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d15c: 52800600 mov w0, #0x30 // #48
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d160: 8b041442 add x2, x2, x4, lsl #5
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d164: 1b007c20 mul w0, w1, w0
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d168: 11013021 add w1, w1, #0x4c
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d16c: d37e1c21 ubfiz x1, x1, #2, #8
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d170: 11006005 add w5, w0, #0x18
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d174: b8656865 ldr w5, [x3, x5]
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d178: 12003ca4 and w4, w5, #0xffff
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d17c: b9024444 str w4, [x2, #580]
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d180: 11001004 add w4, w0, #0x4
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d184: 11009000 add w0, w0, #0x24
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d188: b8646865 ldr w5, [x3, x4]
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d18c: 120010a5 and w5, w5, #0x1f
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d190: b9024045 str w5, [x2, #576]
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d194: 52a003e5 mov w5, #0x1f0000 // #2031616
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d198: b8246865 str w5, [x3, x4]
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d19c: 5285ffe5 mov w5, #0x2fff // #12287
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d1a0: b8606864 ldr w4, [x3, x0]
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d1a4: 0a050084 and w4, w4, w5
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d1a8: b9024844 str w4, [x2, #584]
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d1ac: 5281ffe4 mov w4, #0xfff // #4095
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d1b0: 72a5ffe4 movk w4, #0x2fff, lsl #16
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d1b4: b8206864 str w4, [x3, x0]
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d1b8: b8616860 ldr w0, [x3, x1]
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d1bc: 12120000 and w0, w0, #0x4000
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d1c0: b9024c40 str w0, [x2, #588]
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d1c4: 52a80000 mov w0, #0x40000000 // #1073741824
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d1c8: b8216860 str w0, [x3, x1]
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d1cc: d65f03c0 ret
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