Markus Fritsche
2b68134925
- Strip the perf-trace debug instrumentation (dbg_* counters + HWSUB/rkopnu-trace dev_err); it served its purpose (proved the drm_sched glue is ~3% of a submit). No functional change. - README.md: full build+setup guide (kernel requirements, DT enablement, rocket blacklist, out-of-tree build, librknnrt + rk-llama.cpp rknpu2 userspace, perf notes, limitations). - dt/rk3588-npu-enable.dtso: the necessary DT patch -- mainline ships the RKNN cores + IOMMUs status=disabled; this enables them + OPP table (example board: CoolPi CM5 GenBook; supplies are board-specific). - config/rkopnu.config: kernel config fragment (DRM_ACCEL etc.). - LICENSE: GPL-2.0. A third party can now recreate the mainline-NPU stack from this repo alone.
94 lines
2.2 KiB
Plaintext
94 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* RK3588 NPU enablement overlay for rkopnu (example: CoolPi CM5 GenBook).
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*
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* Mainline ships the three RKNN cores + IOMMUs status = "disabled". This
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* overlay enables them and attaches a DVFS OPP table (vendor V/f pairs,
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* 300 MHz-1 GHz). Apply it (extlinux `fdtoverlays`, U-Boot `fdt apply`, or
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* fold the changes into your board .dts) to bring the NPU up for rkopnu.
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*
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* BOARD-SPECIFIC: point npu-supply/sram-supply at YOUR board's NPU regulator
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* (commonly vdd_npu_s0) and make sure &pd_npu has a domain-supply (most RK3588
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* board DTs already wire this). Deleting assigned-clock-rates lets the driver's
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* OPP DVFS own the NPU clock. Node labels (rknn_core_0.., rknn_mmu_0..) are the
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* mainline rk3588-base.dtsi labels.
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*/
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/dts-v1/;
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/plugin/;
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&{/} {
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npu_opp_table: opp-table-npu {
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compatible = "operating-points-v2";
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <700000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <700000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <700000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <700000>;
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};
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opp-700000000 {
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opp-hz = /bits/ 64 <700000000>;
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opp-microvolt = <700000>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <750000>;
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};
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <800000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <850000>;
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};
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};
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};
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&rknn_core_0 {
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npu-supply = <&vdd_npu_s0>;
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sram-supply = <&vdd_npu_s0>;
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operating-points-v2 = <&npu_opp_table>;
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/delete-property/ assigned-clock-rates;
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status = "okay";
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};
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&rknn_core_1 {
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npu-supply = <&vdd_npu_s0>;
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sram-supply = <&vdd_npu_s0>;
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operating-points-v2 = <&npu_opp_table>;
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/delete-property/ assigned-clock-rates;
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status = "okay";
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};
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&rknn_core_2 {
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npu-supply = <&vdd_npu_s0>;
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sram-supply = <&vdd_npu_s0>;
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operating-points-v2 = <&npu_opp_table>;
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/delete-property/ assigned-clock-rates;
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status = "okay";
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};
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&rknn_mmu_0 {
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status = "okay";
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};
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&rknn_mmu_1 {
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status = "okay";
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};
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&rknn_mmu_2 {
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status = "okay";
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};
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