// ============ REGCMD PACKING ============
// Each register command is one uint64_t:  (target<<48) | (value<<16) | reg
// where target = block_enum + 1.  Block enums:
//   PC=0x100  CNA=0x200  CORE=0x800  DPU=0x1000
// So CNA registers pack with target 0x201, DPU registers with target 0x1001.
// A field is set as:  (value << FIELD__SHIFT) & FIELD__MASK  and OR'd together.

// ============ REGISTER + FIELD DEFINES (from Mesa rkt_registers.h) ============
#define REG_CNA_S_STATUS					0x00001000
#define CNA_S_STATUS_RESERVED_0__MASK				0xfffc0000
#define CNA_S_STATUS_RESERVED_0__SHIFT				18
#define CNA_S_STATUS_STATUS_1__MASK				0x00030000
#define CNA_S_STATUS_STATUS_1__SHIFT				16
#define CNA_S_STATUS_RESERVED_1__MASK				0x0000fffc
#define CNA_S_STATUS_RESERVED_1__SHIFT				2
#define CNA_S_STATUS_STATUS_0__MASK				0x00000003
#define CNA_S_STATUS_STATUS_0__SHIFT				0
#define REG_CNA_S_POINTER					0x00001004
#define CNA_S_POINTER_RESERVED_0__MASK				0xfffe0000
#define CNA_S_POINTER_RESERVED_0__SHIFT				17
#define CNA_S_POINTER_EXECUTER__MASK				0x00010000
#define CNA_S_POINTER_EXECUTER__SHIFT				16
#define CNA_S_POINTER_RESERVED_1__MASK				0x0000ffc0
#define CNA_S_POINTER_RESERVED_1__SHIFT				6
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
#define CNA_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
#define CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
#define CNA_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
#define CNA_S_POINTER_POINTER_PP_MODE__SHIFT			3
#define CNA_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
#define CNA_S_POINTER_EXECUTER_PP_EN__SHIFT			2
#define CNA_S_POINTER_POINTER_PP_EN__MASK			0x00000002
#define CNA_S_POINTER_POINTER_PP_EN__SHIFT			1
#define CNA_S_POINTER_POINTER__MASK				0x00000001
#define CNA_S_POINTER_POINTER__SHIFT				0
#define REG_CNA_OPERATION_ENABLE				0x00001008
#define CNA_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
#define CNA_OPERATION_ENABLE_RESERVED_0__SHIFT			1
#define CNA_OPERATION_ENABLE_OP_EN__MASK			0x00000001
#define CNA_OPERATION_ENABLE_OP_EN__SHIFT			0
#define REG_CNA_CONV_CON1					0x0000100c
#define CNA_CONV_CON1_RESERVED_0__MASK				0x80000000
#define CNA_CONV_CON1_RESERVED_0__SHIFT				31
#define CNA_CONV_CON1_NONALIGN_DMA__MASK			0x40000000
#define CNA_CONV_CON1_NONALIGN_DMA__SHIFT			30
#define CNA_CONV_CON1_GROUP_LINE_OFF__MASK			0x20000000
#define CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT			29
#define CNA_CONV_CON1_RESERVED_1__MASK				0x1ffe0000
#define CNA_CONV_CON1_RESERVED_1__SHIFT				17
#define CNA_CONV_CON1_DECONV__MASK				0x00010000
#define CNA_CONV_CON1_DECONV__SHIFT				16
#define CNA_CONV_CON1_ARGB_IN__MASK				0x0000f000
#define CNA_CONV_CON1_ARGB_IN__SHIFT				12
#define CNA_CONV_CON1_RESERVED_2__MASK				0x00000c00
#define CNA_CONV_CON1_RESERVED_2__SHIFT				10
#define CNA_CONV_CON1_PROC_PRECISION__MASK			0x00000380
#define CNA_CONV_CON1_PROC_PRECISION__SHIFT			7
#define CNA_CONV_CON1_IN_PRECISION__MASK			0x00000070
#define CNA_CONV_CON1_IN_PRECISION__SHIFT			4
#define CNA_CONV_CON1_CONV_MODE__MASK				0x0000000f
#define CNA_CONV_CON1_CONV_MODE__SHIFT				0
#define REG_CNA_CONV_CON2					0x00001010
#define CNA_CONV_CON2_RESERVED_0__MASK				0xff000000
#define CNA_CONV_CON2_RESERVED_0__SHIFT				24
#define CNA_CONV_CON2_KERNEL_GROUP__MASK			0x00ff0000
#define CNA_CONV_CON2_KERNEL_GROUP__SHIFT			16
#define CNA_CONV_CON2_RESERVED_1__MASK				0x0000c000
#define CNA_CONV_CON2_RESERVED_1__SHIFT				14
#define CNA_CONV_CON2_FEATURE_GRAINS__MASK			0x00003ff0
#define CNA_CONV_CON2_FEATURE_GRAINS__SHIFT			4
#define CNA_CONV_CON2_RESERVED_2__MASK				0x00000008
#define CNA_CONV_CON2_RESERVED_2__SHIFT				3
#define CNA_CONV_CON2_CSC_WO_EN__MASK				0x00000004
#define CNA_CONV_CON2_CSC_WO_EN__SHIFT				2
#define CNA_CONV_CON2_CSC_DO_EN__MASK				0x00000002
#define CNA_CONV_CON2_CSC_DO_EN__SHIFT				1
#define CNA_CONV_CON2_CMD_FIFO_SRST__MASK			0x00000001
#define CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT			0
#define REG_CNA_CONV_CON3					0x00001014
#define CNA_CONV_CON3_RESERVED_0__MASK				0x80000000
#define CNA_CONV_CON3_RESERVED_0__SHIFT				31
#define CNA_CONV_CON3_NN_MODE__MASK				0x70000000
#define CNA_CONV_CON3_NN_MODE__SHIFT				28
#define CNA_CONV_CON3_RESERVED_1__MASK				0x0c000000
#define CNA_CONV_CON3_RESERVED_1__SHIFT				26
#define CNA_CONV_CON3_ATROUS_Y_DILATION__MASK			0x03e00000
#define CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT			21
#define CNA_CONV_CON3_ATROUS_X_DILATION__MASK			0x001f0000
#define CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT			16
#define CNA_CONV_CON3_RESERVED_2__MASK				0x0000c000
#define CNA_CONV_CON3_RESERVED_2__SHIFT				14
#define CNA_CONV_CON3_DECONV_Y_STRIDE__MASK			0x00003800
#define CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT			11
#define CNA_CONV_CON3_DECONV_X_STRIDE__MASK			0x00000700
#define CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT			8
#define CNA_CONV_CON3_RESERVED_3__MASK				0x000000c0
#define CNA_CONV_CON3_RESERVED_3__SHIFT				6
#define CNA_CONV_CON3_CONV_Y_STRIDE__MASK			0x00000038
#define CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT			3
#define CNA_CONV_CON3_CONV_X_STRIDE__MASK			0x00000007
#define CNA_CONV_CON3_CONV_X_STRIDE__SHIFT			0
#define REG_CNA_DATA_SIZE0					0x00001020
#define CNA_DATA_SIZE0_RESERVED_0__MASK				0xf8000000
#define CNA_DATA_SIZE0_RESERVED_0__SHIFT			27
#define CNA_DATA_SIZE0_DATAIN_WIDTH__MASK			0x07ff0000
#define CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT			16
#define CNA_DATA_SIZE0_RESERVED_1__MASK				0x0000f800
#define CNA_DATA_SIZE0_RESERVED_1__SHIFT			11
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK			0x000007ff
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT			0
#define REG_CNA_DATA_SIZE1					0x00001024
#define CNA_DATA_SIZE1_RESERVED_0__MASK				0xc0000000
#define CNA_DATA_SIZE1_RESERVED_0__SHIFT			30
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK		0x3fff0000
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT		16
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK			0x0000ffff
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT			0
#define REG_CNA_DATA_SIZE2					0x00001028
#define CNA_DATA_SIZE2_RESERVED_0__MASK				0xfffff800
#define CNA_DATA_SIZE2_RESERVED_0__SHIFT			11
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK			0x000007ff
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT			0
#define REG_CNA_DATA_SIZE3					0x0000102c
#define CNA_DATA_SIZE3_RESERVED_0__MASK				0xff000000
#define CNA_DATA_SIZE3_RESERVED_0__SHIFT			24
#define CNA_DATA_SIZE3_SURF_MODE__MASK				0x00c00000
#define CNA_DATA_SIZE3_SURF_MODE__SHIFT				22
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK			0x003fffff
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT			0
#define REG_CNA_WEIGHT_SIZE0					0x00001030
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK			0xffffffff
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT			0
#define REG_CNA_WEIGHT_SIZE1					0x00001034
#define CNA_WEIGHT_SIZE1_RESERVED_0__MASK			0xfff80000
#define CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT			19
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK		0x0007ffff
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT		0
#define REG_CNA_WEIGHT_SIZE2					0x00001038
#define CNA_WEIGHT_SIZE2_RESERVED_0__MASK			0xe0000000
#define CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT			29
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK			0x1f000000
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT			24
#define CNA_WEIGHT_SIZE2_RESERVED_1__MASK			0x00e00000
#define CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT			21
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK			0x001f0000
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT			16
#define CNA_WEIGHT_SIZE2_RESERVED_2__MASK			0x0000c000
#define CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT			14
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK			0x00003fff
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT			0
#define REG_CNA_CBUF_CON0					0x00001040
#define CNA_CBUF_CON0_RESERVED_0__MASK				0xffffc000
#define CNA_CBUF_CON0_RESERVED_0__SHIFT				14
#define CNA_CBUF_CON0_WEIGHT_REUSE__MASK			0x00002000
#define CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT			13
#define CNA_CBUF_CON0_DATA_REUSE__MASK				0x00001000
#define CNA_CBUF_CON0_DATA_REUSE__SHIFT				12
#define CNA_CBUF_CON0_RESERVED_1__MASK				0x00000800
#define CNA_CBUF_CON0_RESERVED_1__SHIFT				11
#define CNA_CBUF_CON0_FC_DATA_BANK__MASK			0x00000700
#define CNA_CBUF_CON0_FC_DATA_BANK__SHIFT			8
#define CNA_CBUF_CON0_WEIGHT_BANK__MASK				0x000000f0
#define CNA_CBUF_CON0_WEIGHT_BANK__SHIFT			4
#define CNA_CBUF_CON0_DATA_BANK__MASK				0x0000000f
#define CNA_CBUF_CON0_DATA_BANK__SHIFT				0
#define REG_CNA_CBUF_CON1					0x00001044
#define CNA_CBUF_CON1_RESERVED_0__MASK				0xffffc000
#define CNA_CBUF_CON1_RESERVED_0__SHIFT				14
#define CNA_CBUF_CON1_DATA_ENTRIES__MASK			0x00003fff
#define CNA_CBUF_CON1_DATA_ENTRIES__SHIFT			0
#define REG_CNA_CVT_CON0					0x0000104c
#define CNA_CVT_CON0_RESERVED_0__MASK				0xf0000000
#define CNA_CVT_CON0_RESERVED_0__SHIFT				28
#define CNA_CVT_CON0_CVT_TRUNCATE_3__MASK			0x0fc00000
#define CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT			22
#define CNA_CVT_CON0_CVT_TRUNCATE_2__MASK			0x003f0000
#define CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT			16
#define CNA_CVT_CON0_CVT_TRUNCATE_1__MASK			0x0000fc00
#define CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT			10
#define CNA_CVT_CON0_CVT_TRUNCATE_0__MASK			0x000003f0
#define CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT			4
#define CNA_CVT_CON0_DATA_SIGN__MASK				0x00000008
#define CNA_CVT_CON0_DATA_SIGN__SHIFT				3
#define CNA_CVT_CON0_ROUND_TYPE__MASK				0x00000004
#define CNA_CVT_CON0_ROUND_TYPE__SHIFT				2
#define CNA_CVT_CON0_CVT_TYPE__MASK				0x00000002
#define CNA_CVT_CON0_CVT_TYPE__SHIFT				1
#define CNA_CVT_CON0_CVT_BYPASS__MASK				0x00000001
#define CNA_CVT_CON0_CVT_BYPASS__SHIFT				0
#define REG_CNA_CVT_CON1					0x00001050
#define CNA_CVT_CON1_CVT_SCALE0__MASK				0xffff0000
#define CNA_CVT_CON1_CVT_SCALE0__SHIFT				16
#define CNA_CVT_CON1_CVT_OFFSET0__MASK				0x0000ffff
#define CNA_CVT_CON1_CVT_OFFSET0__SHIFT				0
#define REG_CNA_CVT_CON2					0x00001054
#define CNA_CVT_CON2_CVT_SCALE1__MASK				0xffff0000
#define CNA_CVT_CON2_CVT_SCALE1__SHIFT				16
#define CNA_CVT_CON2_CVT_OFFSET1__MASK				0x0000ffff
#define CNA_CVT_CON2_CVT_OFFSET1__SHIFT				0
#define REG_CNA_CVT_CON3					0x00001058
#define CNA_CVT_CON3_CVT_SCALE2__MASK				0xffff0000
#define CNA_CVT_CON3_CVT_SCALE2__SHIFT				16
#define CNA_CVT_CON3_CVT_OFFSET2__MASK				0x0000ffff
#define CNA_CVT_CON3_CVT_OFFSET2__SHIFT				0
#define REG_CNA_CVT_CON4					0x0000105c
#define CNA_CVT_CON4_CVT_SCALE3__MASK				0xffff0000
#define CNA_CVT_CON4_CVT_SCALE3__SHIFT				16
#define CNA_CVT_CON4_CVT_OFFSET3__MASK				0x0000ffff
#define CNA_CVT_CON4_CVT_OFFSET3__SHIFT				0
#define REG_CNA_FC_CON0						0x00001060
#define CNA_FC_CON0_FC_SKIP_DATA__MASK				0xffff0000
#define CNA_FC_CON0_FC_SKIP_DATA__SHIFT				16
#define CNA_FC_CON0_RESERVED_0__MASK				0x0000fffe
#define CNA_FC_CON0_RESERVED_0__SHIFT				1
#define CNA_FC_CON0_FC_SKIP_EN__MASK				0x00000001
#define CNA_FC_CON0_FC_SKIP_EN__SHIFT				0
#define REG_CNA_FC_CON1						0x00001064
#define CNA_FC_CON1_RESERVED_0__MASK				0xfffe0000
#define CNA_FC_CON1_RESERVED_0__SHIFT				17
#define CNA_FC_CON1_DATA_OFFSET__MASK				0x0001ffff
#define CNA_FC_CON1_DATA_OFFSET__SHIFT				0
#define REG_CNA_PAD_CON0					0x00001068
#define CNA_PAD_CON0_RESERVED_0__MASK				0xffffff00
#define CNA_PAD_CON0_RESERVED_0__SHIFT				8
#define CNA_PAD_CON0_PAD_LEFT__MASK				0x000000f0
#define CNA_PAD_CON0_PAD_LEFT__SHIFT				4
#define CNA_PAD_CON0_PAD_TOP__MASK				0x0000000f
#define CNA_PAD_CON0_PAD_TOP__SHIFT				0
#define REG_CNA_FEATURE_DATA_ADDR				0x00001070
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK		0xffffffff
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT		0
#define REG_CNA_FC_CON2						0x00001074
#define CNA_FC_CON2_RESERVED_0__MASK				0xfffe0000
#define CNA_FC_CON2_RESERVED_0__SHIFT				17
#define CNA_FC_CON2_WEIGHT_OFFSET__MASK				0x0001ffff
#define CNA_FC_CON2_WEIGHT_OFFSET__SHIFT			0
#define REG_CNA_DMA_CON0					0x00001078
#define CNA_DMA_CON0_OV4K_BYPASS__MASK				0x80000000
#define CNA_DMA_CON0_OV4K_BYPASS__SHIFT				31
#define CNA_DMA_CON0_RESERVED_0__MASK				0x7ff00000
#define CNA_DMA_CON0_RESERVED_0__SHIFT				20
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK			0x000f0000
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT			16
#define CNA_DMA_CON0_RESERVED_1__MASK				0x0000fff0
#define CNA_DMA_CON0_RESERVED_1__SHIFT				4
#define CNA_DMA_CON0_DATA_BURST_LEN__MASK			0x0000000f
#define CNA_DMA_CON0_DATA_BURST_LEN__SHIFT			0
#define REG_CNA_DMA_CON1					0x0000107c
#define CNA_DMA_CON1_RESERVED_0__MASK				0xf0000000
#define CNA_DMA_CON1_RESERVED_0__SHIFT				28
#define CNA_DMA_CON1_LINE_STRIDE__MASK				0x0fffffff
#define CNA_DMA_CON1_LINE_STRIDE__SHIFT				0
#define REG_CNA_DMA_CON2					0x00001080
#define CNA_DMA_CON2_RESERVED_0__MASK				0xf0000000
#define CNA_DMA_CON2_RESERVED_0__SHIFT				28
#define CNA_DMA_CON2_SURF_STRIDE__MASK				0x0fffffff
#define CNA_DMA_CON2_SURF_STRIDE__SHIFT				0
#define REG_CNA_FC_DATA_SIZE0					0x00001084
#define CNA_FC_DATA_SIZE0_RESERVED_0__MASK			0xc0000000
#define CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT			30
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK			0x3fff0000
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT			16
#define CNA_FC_DATA_SIZE0_RESERVED_1__MASK			0x0000f800
#define CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT			11
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK			0x000007ff
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT			0
#define REG_CNA_FC_DATA_SIZE1					0x00001088
#define CNA_FC_DATA_SIZE1_RESERVED_0__MASK			0xffff0000
#define CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT			16
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK			0x0000ffff
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT			0
#define REG_CNA_CLK_GATE					0x00001090
#define CNA_CLK_GATE_RESERVED_0__MASK				0xffffffe0
#define CNA_CLK_GATE_RESERVED_0__SHIFT				5
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK		0x00000010
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT		4
#define CNA_CLK_GATE_RESERVED_1__MASK				0x00000008
#define CNA_CLK_GATE_RESERVED_1__SHIFT				3
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK			0x00000004
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT			2
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK		0x00000002
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT		1
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK		0x00000001
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT		0
#define REG_CNA_DCOMP_CTRL					0x00001100
#define CNA_DCOMP_CTRL_RESERVED_0__MASK				0xfffffff0
#define CNA_DCOMP_CTRL_RESERVED_0__SHIFT			4
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK			0x00000008
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT			3
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK			0x00000007
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT			0
#define REG_CNA_DCOMP_REGNUM					0x00001104
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK			0xffffffff
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT			0
#define REG_CNA_DCOMP_ADDR0					0x00001110
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK			0xffffffff
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT0					0x00001140
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT1					0x00001144
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT2					0x00001148
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT3					0x0000114c
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT4					0x00001150
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT5					0x00001154
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT6					0x00001158
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT7					0x0000115c
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT8					0x00001160
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT9					0x00001164
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT			0
#define REG_CNA_DCOMP_AMOUNT10					0x00001168
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT		0
#define REG_CNA_DCOMP_AMOUNT11					0x0000116c
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT		0
#define REG_CNA_DCOMP_AMOUNT12					0x00001170
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT		0
#define REG_CNA_DCOMP_AMOUNT13					0x00001174
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT		0
#define REG_CNA_DCOMP_AMOUNT14					0x00001178
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT		0
#define REG_CNA_DCOMP_AMOUNT15					0x0000117c
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK			0xffffffff
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT		0
#define REG_CNA_CVT_CON5					0x00001180
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK			0xffffffff
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT			0
#define REG_CNA_PAD_CON1					0x00001184
#define CNA_PAD_CON1_PAD_VALUE__MASK				0xffffffff
#define CNA_PAD_CON1_PAD_VALUE__SHIFT				0
#define REG_DPU_S_POINTER					0x00004004
#define DPU_S_POINTER_RESERVED_0__MASK				0xfffe0000
#define DPU_S_POINTER_RESERVED_0__SHIFT				17
#define DPU_S_POINTER_EXECUTER__MASK				0x00010000
#define DPU_S_POINTER_EXECUTER__SHIFT				16
#define DPU_S_POINTER_RESERVED_1__MASK				0x0000ffc0
#define DPU_S_POINTER_RESERVED_1__SHIFT				6
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
#define DPU_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT			3
#define DPU_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT			2
#define DPU_S_POINTER_POINTER_PP_EN__MASK			0x00000002
#define DPU_S_POINTER_POINTER_PP_EN__SHIFT			1
#define DPU_S_POINTER_POINTER__MASK				0x00000001
#define DPU_S_POINTER_POINTER__SHIFT				0
#define REG_DPU_RDMA_RDMA_S_STATUS				0x00005000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK			0xfffc0000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT		18
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK			0x00030000
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT			16
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK			0x0000fffc
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT		2
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK			0x00000003
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT			0
#define REG_DPU_RDMA_RDMA_S_POINTER				0x00005004
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK		0xfffe0000
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT		17
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK			0x00010000
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT			16
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK		0x0000ffc0
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT		6
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK		0x00000020
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT	5
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK		0x00000010
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT		4
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK		0x00000008
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT		3
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK		0x00000004
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT		2
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK		0x00000002
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT		1
#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK			0x00000001
#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT			0
#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE			0x00005008
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK		0xfffffffe
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT	1
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK		0x00000001
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT		0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH			0x0000500c
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK		0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT		13
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK		0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT		0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT			0x00005010
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK		0xe0000000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT	29
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK	0x1fff0000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT	16
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK		0x0000e000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT	13
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK		0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT		0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL			0x00005014
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK	0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT	13
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK		0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT		0
#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR				0x00005018
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT	0
#define REG_DPU_RDMA_RDMA_BRDMA_CFG				0x0000501c
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK		0xffffffe0
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT		5
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK		0x0000001e
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT		1
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK		0x00000001
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT		0
#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR				0x00005020
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT		0
#define REG_DPU_RDMA_RDMA_NRDMA_CFG				0x00005028
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK		0xffffffe0
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT		5
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK		0x0000001e
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT		1
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK		0x00000001
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT		0
#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR				0x0000502c
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT		0
#define REG_DPU_RDMA_RDMA_ERDMA_CFG				0x00005034
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK		0xc0000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT		30
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK		0x20000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT		29
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK		0x10000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT		28
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK		0x0ffffff0
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT		4
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK		0x0000000c
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT		2
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK		0x00000002
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT		1
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK		0x00000001
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT		0
#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR				0x00005038
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT		0
#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE			0x00005040
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK	0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT	4
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK		0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT		0
#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG			0x00005044
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK		0xfffc0000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT	18
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK	0x00038000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT	15
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK		0x00007800
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT		11
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK		0x00000700
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT		8
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK	0x000000e0
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT	5
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK	0x00000010
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT	4
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK	0x00000008
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT	3
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK		0x00000006
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT		1
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK	0x00000001
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT	0
#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG				0x00005048
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK		0xfff80000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT	19
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK		0x0007c000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT		14
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK		0x00002000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT		13
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK		0x00001000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT		12
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK	0x00000e00
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT	9
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK	0x000001c0
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT	6
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK		0x00000038
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT		3
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK		0x00000007
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT		0
#define REG_DPU_RDMA_RDMA_SURF_NOTCH				0x0000504c
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK		0xfffffff0
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT		4
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT		0
#define REG_DPU_RDMA_RDMA_PAD_CFG				0x00005064
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK			0xffff0000
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT			16
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK			0x0000ff80
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT			7
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK			0x00000070
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT			4
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK			0x00000008
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT			3
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK			0x00000007
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT			0
#define REG_DPU_RDMA_RDMA_WEIGHT				0x00005068
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK			0xff000000
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT			24
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK			0x00ff0000
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT			16
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK			0x0000ff00
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT			8
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK			0x000000ff
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT			0
#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH				0x0000506c
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK		0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT	4
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT		0

// ============ MESA CNA EMIT (fill_first_regcmd, CNA section) ============
// This is the exact upstream code to port. 'regs' is the output array (util_dynarray);
// EMIT(reg,val) => emit(regs,reg,val) => pack (target<<48)|(val<<16)|reg with target=block+1.
// 'task->' and 'operation->' fields become explicit function parameters in your port.
fill_first_regcmd(struct rkt_ml_subgraph *subgraph,
                  const struct rkt_operation *operation,
                  struct util_dynarray *regs, unsigned task_num)
{
   struct split_task *task =
      util_dynarray_element(&operation->tasks, struct split_task, task_num);
   unsigned num_tasks =
      util_dynarray_num_elements(&operation->tasks, struct split_task);
   unsigned output_zero_point = task->output_zero_point;
   unsigned weights_zero_point = task->weights_zero_point;
   unsigned offset = output_zero_point - 0x80;

   uint32_t con0 = CNA_CBUF_CON0_WEIGHT_BANK(task->weights_banks) |
                   CNA_CBUF_CON0_DATA_BANK(task->input_banks);
   if (task_num > 0 && operation->reuse_weights_cbuf)
      con0 |= CNA_CBUF_CON0_WEIGHT_REUSE(1);

   EMIT(REG_CNA_CBUF_CON0, con0);

   EMIT(REG_CNA_DCOMP_REGNUM, 0);
   EMIT(REG_CNA_DCOMP_CTRL, 0);

   uint32_t con1 = 0x0;
   if (task->input_channels_real == 1) {
      con1 |= CNA_CONV_CON1_NONALIGN_DMA(1) | CNA_CONV_CON1_GROUP_LINE_OFF(1) |
              CNA_CONV_CON1_ARGB_IN(8);
   }

   if (operation->depthwise)
      con1 |= CNA_CONV_CON1_CONV_MODE(3);

   EMIT(REG_CNA_CONV_CON1, con1);

   EMIT(REG_DPU_S_POINTER, DPU_S_POINTER_POINTER_PP_MODE(1) |
                              DPU_S_POINTER_EXECUTER_PP_EN(1) |
                              DPU_S_POINTER_POINTER_PP_EN(1));
   EMIT(REG_DPU_RDMA_RDMA_S_POINTER,
        DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(1) |
           DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(1) |
           DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(1));
   EMIT(REG_CNA_CONV_CON1, con1);
   EMIT(REG_CNA_CONV_CON2,
        CNA_CONV_CON2_FEATURE_GRAINS(
           50 + task->stride_y + 1)); /* Magic: Seems to pass the most tests */
   EMIT(REG_CNA_CONV_CON3, CNA_CONV_CON3_CONV_X_STRIDE(task->stride_x) |
                              CNA_CONV_CON3_CONV_Y_STRIDE(task->stride_y));
   EMIT(REG_CNA_DATA_SIZE0,
        CNA_DATA_SIZE0_DATAIN_WIDTH(task->input_width) |
           CNA_DATA_SIZE0_DATAIN_HEIGHT(task->input_height));

   EMIT(REG_CNA_DATA_SIZE1,
        CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL(task->input_channels_real - 1) |
           CNA_DATA_SIZE1_DATAIN_CHANNEL(task->input_channels));

   EMIT(REG_CNA_DATA_SIZE2, CNA_DATA_SIZE2_DATAOUT_WIDTH(task->output_width));
   EMIT(REG_CNA_DATA_SIZE3, CNA_DATA_SIZE3_DATAOUT_ATOMICS(task->atomic_count));
   EMIT(REG_CNA_WEIGHT_SIZE0, task->weights_width * task->weights_height *
                                 task->input_channels * task->weights_kernels);
   EMIT(REG_CNA_WEIGHT_SIZE1,
        task->weights_width * task->weights_height * task->input_channels);
   EMIT(REG_CNA_WEIGHT_SIZE2,
        CNA_WEIGHT_SIZE2_WEIGHT_WIDTH(task->weights_width) |
           CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT(task->weights_height) |
           CNA_WEIGHT_SIZE2_WEIGHT_KERNELS(task->weights_kernels));

   EMIT(REG_CNA_CBUF_CON0, con0);

   EMIT(REG_CNA_CBUF_CON1, CNA_CBUF_CON1_DATA_ENTRIES(task->input_data_entries));

   if (task->input_channels_real == 1) {
      unsigned truncate = 14;
      unsigned scale = 16384;
      unsigned offset = 65408;

      if (operation->addition_input || operation->add_tensor != -1) {
         truncate = 15;
         scale = 32388;
      }

      EMIT(REG_CNA_CVT_CON0, CNA_CVT_CON0_CVT_TRUNCATE_3(truncate) |
                                CNA_CVT_CON0_CVT_TRUNCATE_2(truncate) |
                                CNA_CVT_CON0_CVT_TRUNCATE_1(truncate) |
                                CNA_CVT_CON0_CVT_TRUNCATE_0(truncate));
      EMIT(REG_CNA_CVT_CON1,
           CNA_CVT_CON1_CVT_SCALE0(scale) | CNA_CVT_CON1_CVT_OFFSET0(offset));
      EMIT(REG_CNA_CVT_CON2,
           CNA_CVT_CON2_CVT_SCALE1(scale) | CNA_CVT_CON2_CVT_OFFSET1(offset));
      EMIT(REG_CNA_CVT_CON3,
           CNA_CVT_CON3_CVT_SCALE2(scale) | CNA_CVT_CON3_CVT_OFFSET2(offset));
      EMIT(REG_CNA_CVT_CON4,
           CNA_CVT_CON4_CVT_SCALE3(scale) | CNA_CVT_CON4_CVT_OFFSET3(offset));
   } else {
      EMIT(REG_CNA_CVT_CON0, CNA_CVT_CON0_DATA_SIGN(1) |
                                CNA_CVT_CON0_CVT_TYPE(1) |
                                CNA_CVT_CON0_CVT_BYPASS(1));
      EMIT(REG_CNA_CVT_CON1, CNA_CVT_CON1_CVT_SCALE0(1));
      EMIT(REG_CNA_CVT_CON2, CNA_CVT_CON2_CVT_SCALE1(1));
      EMIT(REG_CNA_CVT_CON3, CNA_CVT_CON3_CVT_SCALE2(1));
      EMIT(REG_CNA_CVT_CON4, CNA_CVT_CON4_CVT_SCALE3(1));
   }

   EMIT(REG_CNA_FC_CON0, 0);
   EMIT(REG_CNA_FC_CON1, 0);
   EMIT(REG_CNA_PAD_CON0, CNA_PAD_CON0_PAD_LEFT(task->pad_left) |
                             CNA_PAD_CON0_PAD_TOP(task->pad_top));
   EMIT(REG_CNA_FEATURE_DATA_ADDR,
        rkt_get_tensor(subgraph, operation->input_index)->phys_addr +
           task->input_offset);
   EMIT(REG_CNA_FC_CON2, 0);
   EMIT(REG_CNA_DMA_CON0,
        CNA_DMA_CON0_WEIGHT_BURST_LEN(15) | CNA_DMA_CON0_DATA_BURST_LEN(15));
   EMIT(REG_CNA_DMA_CON1, CNA_DMA_CON1_LINE_STRIDE(task->input_line_stride));
   EMIT(REG_CNA_DMA_CON2, CNA_DMA_CON2_SURF_STRIDE(task->input_surface_stride));

   EMIT(REG_CNA_FC_DATA_SIZE0,
        CNA_FC_DATA_SIZE0_DMA_WIDTH(operation->input_width) |
           CNA_FC_DATA_SIZE0_DMA_HEIGHT(task->input_height));

   EMIT(REG_CNA_FC_DATA_SIZE1,
        CNA_FC_DATA_SIZE1_DMA_CHANNEL(task->input_channels));
   EMIT(REG_CNA_DCOMP_CTRL, 0);
   EMIT(REG_CNA_DCOMP_REGNUM, 0);
   EMIT(REG_CNA_DCOMP_ADDR0, rkt_resource(operation->weights)->phys_addr);
   EMIT(REG_CNA_DCOMP_AMOUNT0, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT1, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT2, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT3, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT4, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT5, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT6, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT7, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT8, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT9, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT10, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT11, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT12, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT13, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT14, 0);
   EMIT(REG_CNA_DCOMP_AMOUNT15, 0);

   if (task->input_channels_real == 1) {
      EMIT(REG_CNA_CVT_CON5, 65535);
   } else {
      EMIT(REG_CNA_CVT_CON5, 0);
   }

   int32_t pad_con1;
   if (task->weights_width >= 3 && task->input_zero_point == 0x0)
      pad_con1 = 0xffff8080;
   else
      pad_con1 = task->input_zero_point - 0x80;

   if (operation->addition_input || operation->add_tensor != -1)
      pad_con1 = 0xffffff80;

   if (operation->depthwise && task->input_zero_point == 0x8b)
      pad_con1 = 0x0b0b;

   EMIT(REG_CNA_PAD_CON1, pad_con1);

   uint32_t misc_cfg = CORE_MISC_CFG_QD_EN(1);
   if (operation->depthwise)
      misc_cfg |= CORE_MISC_CFG_DW_EN(1);

