// ===== REGCMD PACKING =====
// Each command = uint64_t: (target<<48) | (value<<16) | reg, target = block_enum + 1.
// Blocks: PC=0x100 (target 0x101), CORE=0x800 (target 0x801), DPU=0x1000 (target 0x1001).
// Field set: (value << FIELD__SHIFT) & FIELD__MASK, OR'd.
// NON-MECHANICAL spots to route through struct params (like the CNA stage did):
//   - output DMA addr: rkt_get_tensor(subgraph, operation->output_index)->phys_addr + output_offset
//   - add-tensor DMA addr: rkt_get_tensor(subgraph, operation->add_tensor)->phys_addr + ...
//   - biases DMA addr: rkt_resource(operation->biases)->phys_addr
//   - float scales: task->input_scale, task->weights_scale, task->output_scale, operation->addition_scale (keep the float math, source from struct)

// ===== REGISTER + FIELD DEFINES (from Mesa rkt_registers.h) =====
#define REG_PC_VERSION						0x00000000
#define PC_VERSION_VERSION__MASK				0xffffffff
#define PC_VERSION_VERSION__SHIFT				0
#define REG_PC_VERSION_NUM					0x00000004
#define PC_VERSION_NUM_VERSION_NUM__MASK			0xffffffff
#define PC_VERSION_NUM_VERSION_NUM__SHIFT			0
#define REG_PC_OPERATION_ENABLE					0x00000008
#define PC_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
#define PC_OPERATION_ENABLE_RESERVED_0__SHIFT			1
#define PC_OPERATION_ENABLE_OP_EN__MASK				0x00000001
#define PC_OPERATION_ENABLE_OP_EN__SHIFT			0
#define REG_PC_BASE_ADDRESS					0x00000010
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK			0xfffffff0
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT			4
#define PC_BASE_ADDRESS_RESERVED_0__MASK			0x0000000e
#define PC_BASE_ADDRESS_RESERVED_0__SHIFT			1
#define PC_BASE_ADDRESS_PC_SEL__MASK				0x00000001
#define PC_BASE_ADDRESS_PC_SEL__SHIFT				0
#define REG_PC_REGISTER_AMOUNTS					0x00000014
#define PC_REGISTER_AMOUNTS_RESERVED_0__MASK			0xffff0000
#define PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT			16
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK		0x0000ffff
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT		0
#define REG_PC_INTERRUPT_MASK					0x00000020
#define PC_INTERRUPT_MASK_RESERVED_0__MASK			0xffffc000
#define PC_INTERRUPT_MASK_RESERVED_0__SHIFT			14
#define PC_INTERRUPT_MASK_DMA_WRITE_ERROR			0x00002000
#define PC_INTERRUPT_MASK_DMA_READ_ERROR			0x00001000
#define PC_INTERRUPT_MASK_PPU_1					0x00000800
#define PC_INTERRUPT_MASK_PPU_0					0x00000400
#define PC_INTERRUPT_MASK_DPU_1					0x00000200
#define PC_INTERRUPT_MASK_DPU_0					0x00000100
#define PC_INTERRUPT_MASK_CORE_1				0x00000080
#define PC_INTERRUPT_MASK_CORE_0				0x00000040
#define PC_INTERRUPT_MASK_CNA_CSC_1				0x00000020
#define PC_INTERRUPT_MASK_CNA_CSC_0				0x00000010
#define PC_INTERRUPT_MASK_CNA_WEIGHT_1				0x00000008
#define PC_INTERRUPT_MASK_CNA_WEIGHT_0				0x00000004
#define PC_INTERRUPT_MASK_CNA_FEATURE_1				0x00000002
#define PC_INTERRUPT_MASK_CNA_FEATURE_0				0x00000001
#define REG_PC_INTERRUPT_CLEAR					0x00000024
#define PC_INTERRUPT_CLEAR_RESERVED_0__MASK			0xffffc000
#define PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT			14
#define PC_INTERRUPT_CLEAR_DMA_WRITE_ERROR			0x00002000
#define PC_INTERRUPT_CLEAR_DMA_READ_ERROR			0x00001000
#define PC_INTERRUPT_CLEAR_PPU_1				0x00000800
#define PC_INTERRUPT_CLEAR_PPU_0				0x00000400
#define PC_INTERRUPT_CLEAR_DPU_1				0x00000200
#define PC_INTERRUPT_CLEAR_DPU_0				0x00000100
#define PC_INTERRUPT_CLEAR_CORE_1				0x00000080
#define PC_INTERRUPT_CLEAR_CORE_0				0x00000040
#define PC_INTERRUPT_CLEAR_CNA_CSC_1				0x00000020
#define PC_INTERRUPT_CLEAR_CNA_CSC_0				0x00000010
#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_1				0x00000008
#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_0				0x00000004
#define PC_INTERRUPT_CLEAR_CNA_FEATURE_1			0x00000002
#define PC_INTERRUPT_CLEAR_CNA_FEATURE_0			0x00000001
#define REG_PC_INTERRUPT_STATUS					0x00000028
#define PC_INTERRUPT_STATUS_RESERVED_0__MASK			0xffffc000
#define PC_INTERRUPT_STATUS_RESERVED_0__SHIFT			14
#define PC_INTERRUPT_STATUS_DMA_WRITE_ERROR			0x00002000
#define PC_INTERRUPT_STATUS_DMA_READ_ERROR			0x00001000
#define PC_INTERRUPT_STATUS_PPU_1				0x00000800
#define PC_INTERRUPT_STATUS_PPU_0				0x00000400
#define PC_INTERRUPT_STATUS_DPU_1				0x00000200
#define PC_INTERRUPT_STATUS_DPU_0				0x00000100
#define PC_INTERRUPT_STATUS_CORE_1				0x00000080
#define PC_INTERRUPT_STATUS_CORE_0				0x00000040
#define PC_INTERRUPT_STATUS_CNA_CSC_1				0x00000020
#define PC_INTERRUPT_STATUS_CNA_CSC_0				0x00000010
#define PC_INTERRUPT_STATUS_CNA_WEIGHT_1			0x00000008
#define PC_INTERRUPT_STATUS_CNA_WEIGHT_0			0x00000004
#define PC_INTERRUPT_STATUS_CNA_FEATURE_1			0x00000002
#define PC_INTERRUPT_STATUS_CNA_FEATURE_0			0x00000001
#define REG_PC_INTERRUPT_RAW_STATUS				0x0000002c
#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK		0xffffc000
#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT		14
#define PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR			0x00002000
#define PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR			0x00001000
#define PC_INTERRUPT_RAW_STATUS_PPU_1				0x00000800
#define PC_INTERRUPT_RAW_STATUS_PPU_0				0x00000400
#define PC_INTERRUPT_RAW_STATUS_DPU_1				0x00000200
#define PC_INTERRUPT_RAW_STATUS_DPU_0				0x00000100
#define PC_INTERRUPT_RAW_STATUS_CORE_1				0x00000080
#define PC_INTERRUPT_RAW_STATUS_CORE_0				0x00000040
#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_1			0x00000020
#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_0			0x00000010
#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_1			0x00000008
#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_0			0x00000004
#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_1			0x00000002
#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_0			0x00000001
#define REG_PC_TASK_CON						0x00000030
#define PC_TASK_CON_RESERVED_0__MASK				0xffffc000
#define PC_TASK_CON_RESERVED_0__SHIFT				14
#define PC_TASK_CON_TASK_COUNT_CLEAR__MASK			0x00002000
#define PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT			13
#define PC_TASK_CON_TASK_PP_EN__MASK				0x00001000
#define PC_TASK_CON_TASK_PP_EN__SHIFT				12
#define PC_TASK_CON_TASK_NUMBER__MASK				0x00000fff
#define PC_TASK_CON_TASK_NUMBER__SHIFT				0
#define REG_PC_TASK_DMA_BASE_ADDR				0x00000034
#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK		0xfffffff0
#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT		4
#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK			0x0000000f
#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT			0
#define REG_PC_TASK_STATUS					0x0000003c
#define PC_TASK_STATUS_RESERVED_0__MASK				0xf0000000
#define PC_TASK_STATUS_RESERVED_0__SHIFT			28
#define PC_TASK_STATUS_TASK_STATUS__MASK			0x0fffffff
#define PC_TASK_STATUS_TASK_STATUS__SHIFT			0
#define REG_CORE_S_STATUS					0x00003000
#define CORE_S_STATUS_RESERVED_0__MASK				0xfffc0000
#define CORE_S_STATUS_RESERVED_0__SHIFT				18
#define CORE_S_STATUS_STATUS_1__MASK				0x00030000
#define CORE_S_STATUS_STATUS_1__SHIFT				16
#define CORE_S_STATUS_RESERVED_1__MASK				0x0000fffc
#define CORE_S_STATUS_RESERVED_1__SHIFT				2
#define CORE_S_STATUS_STATUS_0__MASK				0x00000003
#define CORE_S_STATUS_STATUS_0__SHIFT				0
#define REG_CORE_S_POINTER					0x00003004
#define CORE_S_POINTER_RESERVED_0__MASK				0xfffe0000
#define CORE_S_POINTER_RESERVED_0__SHIFT			17
#define CORE_S_POINTER_EXECUTER__MASK				0x00010000
#define CORE_S_POINTER_EXECUTER__SHIFT				16
#define CORE_S_POINTER_RESERVED_1__MASK				0x0000ffc0
#define CORE_S_POINTER_RESERVED_1__SHIFT			6
#define CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
#define CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
#define CORE_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
#define CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
#define CORE_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
#define CORE_S_POINTER_POINTER_PP_MODE__SHIFT			3
#define CORE_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
#define CORE_S_POINTER_EXECUTER_PP_EN__SHIFT			2
#define CORE_S_POINTER_POINTER_PP_EN__MASK			0x00000002
#define CORE_S_POINTER_POINTER_PP_EN__SHIFT			1
#define CORE_S_POINTER_POINTER__MASK				0x00000001
#define CORE_S_POINTER_POINTER__SHIFT				0
#define REG_CORE_OPERATION_ENABLE				0x00003008
#define CORE_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
#define CORE_OPERATION_ENABLE_RESERVED_0__SHIFT			1
#define CORE_OPERATION_ENABLE_OP_EN__MASK			0x00000001
#define CORE_OPERATION_ENABLE_OP_EN__SHIFT			0
#define REG_CORE_MAC_GATING					0x0000300c
#define CORE_MAC_GATING_RESERVED_0__MASK			0xf8000000
#define CORE_MAC_GATING_RESERVED_0__SHIFT			27
#define CORE_MAC_GATING_SLCG_OP_EN__MASK			0x07ffffff
#define CORE_MAC_GATING_SLCG_OP_EN__SHIFT			0
#define REG_CORE_MISC_CFG					0x00003010
#define CORE_MISC_CFG_RESERVED_0__MASK				0xfff00000
#define CORE_MISC_CFG_RESERVED_0__SHIFT				20
#define CORE_MISC_CFG_SOFT_GATING__MASK				0x000fc000
#define CORE_MISC_CFG_SOFT_GATING__SHIFT			14
#define CORE_MISC_CFG_RESERVED_1__MASK				0x00003800
#define CORE_MISC_CFG_RESERVED_1__SHIFT				11
#define CORE_MISC_CFG_PROC_PRECISION__MASK			0x00000700
#define CORE_MISC_CFG_PROC_PRECISION__SHIFT			8
#define CORE_MISC_CFG_RESERVED_2__MASK				0x000000fc
#define CORE_MISC_CFG_RESERVED_2__SHIFT				2
#define CORE_MISC_CFG_DW_EN__MASK				0x00000002
#define CORE_MISC_CFG_DW_EN__SHIFT				1
#define CORE_MISC_CFG_QD_EN__MASK				0x00000001
#define CORE_MISC_CFG_QD_EN__SHIFT				0
#define REG_CORE_DATAOUT_SIZE_0					0x00003014
#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK		0xffff0000
#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT		16
#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK			0x0000ffff
#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT		0
#define REG_CORE_DATAOUT_SIZE_1					0x00003018
#define CORE_DATAOUT_SIZE_1_RESERVED_0__MASK			0xffff0000
#define CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT			16
#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK		0x0000ffff
#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT		0
#define REG_CORE_CLIP_TRUNCATE					0x0000301c
#define CORE_CLIP_TRUNCATE_RESERVED_0__MASK			0xffffff80
#define CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT			7
#define CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK			0x00000040
#define CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT			6
#define CORE_CLIP_TRUNCATE_RESERVED_1__MASK			0x00000020
#define CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT			5
#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK			0x0000001f
#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT			0
#define REG_DPU_S_STATUS					0x00004000
#define DPU_S_STATUS_RESERVED_0__MASK				0xfffc0000
#define DPU_S_STATUS_RESERVED_0__SHIFT				18
#define DPU_S_STATUS_STATUS_1__MASK				0x00030000
#define DPU_S_STATUS_STATUS_1__SHIFT				16
#define DPU_S_STATUS_RESERVED_1__MASK				0x0000fffc
#define DPU_S_STATUS_RESERVED_1__SHIFT				2
#define DPU_S_STATUS_STATUS_0__MASK				0x00000003
#define DPU_S_STATUS_STATUS_0__SHIFT				0
#define REG_DPU_S_POINTER					0x00004004
#define DPU_S_POINTER_RESERVED_0__MASK				0xfffe0000
#define DPU_S_POINTER_RESERVED_0__SHIFT				17
#define DPU_S_POINTER_EXECUTER__MASK				0x00010000
#define DPU_S_POINTER_EXECUTER__SHIFT				16
#define DPU_S_POINTER_RESERVED_1__MASK				0x0000ffc0
#define DPU_S_POINTER_RESERVED_1__SHIFT				6
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK			0x00000020
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT			5
#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK			0x00000010
#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT			4
#define DPU_S_POINTER_POINTER_PP_MODE__MASK			0x00000008
#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT			3
#define DPU_S_POINTER_EXECUTER_PP_EN__MASK			0x00000004
#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT			2
#define DPU_S_POINTER_POINTER_PP_EN__MASK			0x00000002
#define DPU_S_POINTER_POINTER_PP_EN__SHIFT			1
#define DPU_S_POINTER_POINTER__MASK				0x00000001
#define DPU_S_POINTER_POINTER__SHIFT				0
#define REG_DPU_OPERATION_ENABLE				0x00004008
#define DPU_OPERATION_ENABLE_RESERVED_0__MASK			0xfffffffe
#define DPU_OPERATION_ENABLE_RESERVED_0__SHIFT			1
#define DPU_OPERATION_ENABLE_OP_EN__MASK			0x00000001
#define DPU_OPERATION_ENABLE_OP_EN__SHIFT			0
#define REG_DPU_FEATURE_MODE_CFG				0x0000400c
#define DPU_FEATURE_MODE_CFG_COMB_USE__MASK			0x80000000
#define DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT			31
#define DPU_FEATURE_MODE_CFG_TP_EN__MASK			0x40000000
#define DPU_FEATURE_MODE_CFG_TP_EN__SHIFT			30
#define DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK			0x3c000000
#define DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT			26
#define DPU_FEATURE_MODE_CFG_NONALIGN__MASK			0x02000000
#define DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT			25
#define DPU_FEATURE_MODE_CFG_SURF_LEN__MASK			0x01fffe00
#define DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT			9
#define DPU_FEATURE_MODE_CFG_BURST_LEN__MASK			0x000001e0
#define DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT			5
#define DPU_FEATURE_MODE_CFG_CONV_MODE__MASK			0x00000018
#define DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT			3
#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK			0x00000006
#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT			1
#define DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK			0x00000001
#define DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT			0
#define REG_DPU_DATA_FORMAT					0x00004010
#define DPU_DATA_FORMAT_OUT_PRECISION__MASK			0xe0000000
#define DPU_DATA_FORMAT_OUT_PRECISION__SHIFT			29
#define DPU_DATA_FORMAT_IN_PRECISION__MASK			0x1c000000
#define DPU_DATA_FORMAT_IN_PRECISION__SHIFT			26
#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK			0x03ff0000
#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT			16
#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK		0x0000fc00
#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT		10
#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK		0x000003f0
#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT		4
#define DPU_DATA_FORMAT_MC_SURF_OUT__MASK			0x00000008
#define DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT			3
#define DPU_DATA_FORMAT_PROC_PRECISION__MASK			0x00000007
#define DPU_DATA_FORMAT_PROC_PRECISION__SHIFT			0
#define REG_DPU_OFFSET_PEND					0x00004014
#define DPU_OFFSET_PEND_RESERVED_0__MASK			0xffff0000
#define DPU_OFFSET_PEND_RESERVED_0__SHIFT			16
#define DPU_OFFSET_PEND_OFFSET_PEND__MASK			0x0000ffff
#define DPU_OFFSET_PEND_OFFSET_PEND__SHIFT			0
#define REG_DPU_DST_BASE_ADDR					0x00004020
#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK			0xffffffff
#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT			0
#define REG_DPU_DST_SURF_STRIDE					0x00004024
#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK		0xfffffff0
#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT		4
#define DPU_DST_SURF_STRIDE_RESERVED_0__MASK			0x0000000f
#define DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT			0
#define REG_DPU_DATA_CUBE_WIDTH					0x00004030
#define DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK			0xffffe000
#define DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT			13
#define DPU_DATA_CUBE_WIDTH_WIDTH__MASK				0x00001fff
#define DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT			0
#define REG_DPU_DATA_CUBE_HEIGHT				0x00004034
#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK			0xfe000000
#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT			25
#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK			0x01c00000
#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT			22
#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK			0x003fe000
#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT			13
#define DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK			0x00001fff
#define DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT			0
#define REG_DPU_DATA_CUBE_NOTCH_ADDR				0x00004038
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK		0xe0000000
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT		29
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK		0x1fff0000
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT		16
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK		0x0000e000
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT		13
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK		0x00001fff
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT		0
#define REG_DPU_DATA_CUBE_CHANNEL				0x0000403c
#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK			0xe0000000
#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT			29
#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK		0x1fff0000
#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT		16
#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK			0x0000e000
#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT			13
#define DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK			0x00001fff
#define DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT			0
#define REG_DPU_BS_CFG						0x00004040
#define DPU_BS_CFG_RESERVED_0__MASK				0xfff00000
#define DPU_BS_CFG_RESERVED_0__SHIFT				20
#define DPU_BS_CFG_BS_ALU_ALGO__MASK				0x000f0000
#define DPU_BS_CFG_BS_ALU_ALGO__SHIFT				16
#define DPU_BS_CFG_RESERVED_1__MASK				0x0000fe00
#define DPU_BS_CFG_RESERVED_1__SHIFT				9
#define DPU_BS_CFG_BS_ALU_SRC__MASK				0x00000100
#define DPU_BS_CFG_BS_ALU_SRC__SHIFT				8
#define DPU_BS_CFG_BS_RELUX_EN__MASK				0x00000080
#define DPU_BS_CFG_BS_RELUX_EN__SHIFT				7
#define DPU_BS_CFG_BS_RELU_BYPASS__MASK				0x00000040
#define DPU_BS_CFG_BS_RELU_BYPASS__SHIFT			6
#define DPU_BS_CFG_BS_MUL_PRELU__MASK				0x00000020
#define DPU_BS_CFG_BS_MUL_PRELU__SHIFT				5
#define DPU_BS_CFG_BS_MUL_BYPASS__MASK				0x00000010
#define DPU_BS_CFG_BS_MUL_BYPASS__SHIFT				4
#define DPU_BS_CFG_RESERVED_2__MASK				0x0000000c
#define DPU_BS_CFG_RESERVED_2__SHIFT				2
#define DPU_BS_CFG_BS_ALU_BYPASS__MASK				0x00000002
#define DPU_BS_CFG_BS_ALU_BYPASS__SHIFT				1
#define DPU_BS_CFG_BS_BYPASS__MASK				0x00000001
#define DPU_BS_CFG_BS_BYPASS__SHIFT				0
#define REG_DPU_BS_ALU_CFG					0x00004044
#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK			0xffffffff
#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT			0
#define REG_DPU_BS_MUL_CFG					0x00004048
#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK			0xffff0000
#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT			16
#define DPU_BS_MUL_CFG_RESERVED_0__MASK				0x0000c000
#define DPU_BS_MUL_CFG_RESERVED_0__SHIFT			14
#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK			0x00003f00
#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT		8
#define DPU_BS_MUL_CFG_RESERVED_1__MASK				0x000000fc
#define DPU_BS_MUL_CFG_RESERVED_1__SHIFT			2
#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK			0x00000002
#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT			1
#define DPU_BS_MUL_CFG_BS_MUL_SRC__MASK				0x00000001
#define DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT			0
#define REG_DPU_BS_RELUX_CMP_VALUE				0x0000404c
#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK		0xffffffff
#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT		0
#define REG_DPU_BS_OW_CFG					0x00004050
#define DPU_BS_OW_CFG_RGP_CNTER__MASK				0xf0000000
#define DPU_BS_OW_CFG_RGP_CNTER__SHIFT				28
#define DPU_BS_OW_CFG_TP_ORG_EN__MASK				0x08000000
#define DPU_BS_OW_CFG_TP_ORG_EN__SHIFT				27
#define DPU_BS_OW_CFG_RESERVED_0__MASK				0x07fff800
#define DPU_BS_OW_CFG_RESERVED_0__SHIFT				11
#define DPU_BS_OW_CFG_SIZE_E_2__MASK				0x00000700
#define DPU_BS_OW_CFG_SIZE_E_2__SHIFT				8
#define DPU_BS_OW_CFG_SIZE_E_1__MASK				0x000000e0
#define DPU_BS_OW_CFG_SIZE_E_1__SHIFT				5
#define DPU_BS_OW_CFG_SIZE_E_0__MASK				0x0000001c
#define DPU_BS_OW_CFG_SIZE_E_0__SHIFT				2
#define DPU_BS_OW_CFG_OD_BYPASS__MASK				0x00000002
#define DPU_BS_OW_CFG_OD_BYPASS__SHIFT				1
#define DPU_BS_OW_CFG_OW_SRC__MASK				0x00000001
#define DPU_BS_OW_CFG_OW_SRC__SHIFT				0
#define REG_DPU_BS_OW_OP					0x00004054
#define DPU_BS_OW_OP_RESERVED_0__MASK				0xffff0000
#define DPU_BS_OW_OP_RESERVED_0__SHIFT				16
#define DPU_BS_OW_OP_OW_OP__MASK				0x0000ffff
#define DPU_BS_OW_OP_OW_OP__SHIFT				0
#define REG_DPU_WDMA_SIZE_0					0x00004058
#define DPU_WDMA_SIZE_0_RESERVED_0__MASK			0xf0000000
#define DPU_WDMA_SIZE_0_RESERVED_0__SHIFT			28
#define DPU_WDMA_SIZE_0_TP_PRECISION__MASK			0x08000000
#define DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT			27
#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK			0x07ff0000
#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT			16
#define DPU_WDMA_SIZE_0_RESERVED_1__MASK			0x0000e000
#define DPU_WDMA_SIZE_0_RESERVED_1__SHIFT			13
#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK			0x00001fff
#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT			0
#define REG_DPU_WDMA_SIZE_1					0x0000405c
#define DPU_WDMA_SIZE_1_RESERVED_0__MASK			0xe0000000
#define DPU_WDMA_SIZE_1_RESERVED_0__SHIFT			29
#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK			0x1fff0000
#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT			16
#define DPU_WDMA_SIZE_1_RESERVED_1__MASK			0x0000e000
#define DPU_WDMA_SIZE_1_RESERVED_1__SHIFT			13
#define DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK			0x00001fff
#define DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT			0
#define REG_DPU_BN_CFG						0x00004060
#define DPU_BN_CFG_RESERVED_0__MASK				0xfff00000
#define DPU_BN_CFG_RESERVED_0__SHIFT				20
#define DPU_BN_CFG_BN_ALU_ALGO__MASK				0x000f0000
#define DPU_BN_CFG_BN_ALU_ALGO__SHIFT				16
#define DPU_BN_CFG_RESERVED_1__MASK				0x0000fe00
#define DPU_BN_CFG_RESERVED_1__SHIFT				9
#define DPU_BN_CFG_BN_ALU_SRC__MASK				0x00000100
#define DPU_BN_CFG_BN_ALU_SRC__SHIFT				8
#define DPU_BN_CFG_BN_RELUX_EN__MASK				0x00000080
#define DPU_BN_CFG_BN_RELUX_EN__SHIFT				7
#define DPU_BN_CFG_BN_RELU_BYPASS__MASK				0x00000040
#define DPU_BN_CFG_BN_RELU_BYPASS__SHIFT			6
#define DPU_BN_CFG_BN_MUL_PRELU__MASK				0x00000020
#define DPU_BN_CFG_BN_MUL_PRELU__SHIFT				5
#define DPU_BN_CFG_BN_MUL_BYPASS__MASK				0x00000010
#define DPU_BN_CFG_BN_MUL_BYPASS__SHIFT				4
#define DPU_BN_CFG_RESERVED_2__MASK				0x0000000c
#define DPU_BN_CFG_RESERVED_2__SHIFT				2
#define DPU_BN_CFG_BN_ALU_BYPASS__MASK				0x00000002
#define DPU_BN_CFG_BN_ALU_BYPASS__SHIFT				1
#define DPU_BN_CFG_BN_BYPASS__MASK				0x00000001
#define DPU_BN_CFG_BN_BYPASS__SHIFT				0
#define REG_DPU_BN_ALU_CFG					0x00004064
#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK			0xffffffff
#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT			0
#define REG_DPU_BN_MUL_CFG					0x00004068
#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK			0xffff0000
#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT			16
#define DPU_BN_MUL_CFG_RESERVED_0__MASK				0x0000c000
#define DPU_BN_MUL_CFG_RESERVED_0__SHIFT			14
#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK			0x00003f00
#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT		8
#define DPU_BN_MUL_CFG_RESERVED_1__MASK				0x000000fc
#define DPU_BN_MUL_CFG_RESERVED_1__SHIFT			2
#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK			0x00000002
#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT			1
#define DPU_BN_MUL_CFG_BN_MUL_SRC__MASK				0x00000001
#define DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT			0
#define REG_DPU_BN_RELUX_CMP_VALUE				0x0000406c
#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK		0xffffffff
#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT		0
#define REG_DPU_EW_CFG						0x00004070
#define DPU_EW_CFG_EW_CVT_TYPE__MASK				0x80000000
#define DPU_EW_CFG_EW_CVT_TYPE__SHIFT				31
#define DPU_EW_CFG_EW_CVT_ROUND__MASK				0x40000000
#define DPU_EW_CFG_EW_CVT_ROUND__SHIFT				30
#define DPU_EW_CFG_EW_DATA_MODE__MASK				0x30000000
#define DPU_EW_CFG_EW_DATA_MODE__SHIFT				28
#define DPU_EW_CFG_RESERVED_0__MASK				0x0f000000
#define DPU_EW_CFG_RESERVED_0__SHIFT				24
#define DPU_EW_CFG_EDATA_SIZE__MASK				0x00c00000
#define DPU_EW_CFG_EDATA_SIZE__SHIFT				22
#define DPU_EW_CFG_EW_EQUAL_EN__MASK				0x00200000
#define DPU_EW_CFG_EW_EQUAL_EN__SHIFT				21
#define DPU_EW_CFG_EW_BINARY_EN__MASK				0x00100000
#define DPU_EW_CFG_EW_BINARY_EN__SHIFT				20
#define DPU_EW_CFG_EW_ALU_ALGO__MASK				0x000f0000
#define DPU_EW_CFG_EW_ALU_ALGO__SHIFT				16
#define DPU_EW_CFG_RESERVED_1__MASK				0x0000f800
#define DPU_EW_CFG_RESERVED_1__SHIFT				11
#define DPU_EW_CFG_EW_RELUX_EN__MASK				0x00000400
#define DPU_EW_CFG_EW_RELUX_EN__SHIFT				10
#define DPU_EW_CFG_EW_RELU_BYPASS__MASK				0x00000200
#define DPU_EW_CFG_EW_RELU_BYPASS__SHIFT			9
#define DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK			0x00000100
#define DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT			8
#define DPU_EW_CFG_EW_LUT_BYPASS__MASK				0x00000080
#define DPU_EW_CFG_EW_LUT_BYPASS__SHIFT				7
#define DPU_EW_CFG_EW_OP_SRC__MASK				0x00000040
#define DPU_EW_CFG_EW_OP_SRC__SHIFT				6
#define DPU_EW_CFG_EW_MUL_PRELU__MASK				0x00000020
#define DPU_EW_CFG_EW_MUL_PRELU__SHIFT				5
#define DPU_EW_CFG_RESERVED_2__MASK				0x00000018
#define DPU_EW_CFG_RESERVED_2__SHIFT				3
#define DPU_EW_CFG_EW_OP_TYPE__MASK				0x00000004
#define DPU_EW_CFG_EW_OP_TYPE__SHIFT				2
#define DPU_EW_CFG_EW_OP_BYPASS__MASK				0x00000002
#define DPU_EW_CFG_EW_OP_BYPASS__SHIFT				1
#define DPU_EW_CFG_EW_BYPASS__MASK				0x00000001
#define DPU_EW_CFG_EW_BYPASS__SHIFT				0
#define REG_DPU_EW_CVT_OFFSET_VALUE				0x00004074
#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK		0xffffffff
#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT		0
#define REG_DPU_EW_CVT_SCALE_VALUE				0x00004078
#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK		0xffc00000
#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT		22
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK		0x003f0000
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT		16
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK		0x0000ffff
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT		0
#define REG_DPU_EW_RELUX_CMP_VALUE				0x0000407c
#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK		0xffffffff
#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT		0
#define REG_DPU_OUT_CVT_OFFSET					0x00004080
#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK			0xffffffff
#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT		0
#define REG_DPU_OUT_CVT_SCALE					0x00004084
#define DPU_OUT_CVT_SCALE_RESERVED_0__MASK			0xfffe0000
#define DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT			17
#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK			0x00010000
#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT			16
#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK			0x0000ffff
#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT			0
#define REG_DPU_OUT_CVT_SHIFT					0x00004088
#define DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK			0x80000000
#define DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT			31
#define DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK			0x40000000
#define DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT			30
#define DPU_OUT_CVT_SHIFT_RESERVED_0__MASK			0x3ff00000
#define DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT			20
#define DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK			0x000ff000
#define DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT			12
#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK			0x00000fff
#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT			0
#define REG_DPU_EW_OP_VALUE_0					0x00004090
#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK			0xffffffff
#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT			0
#define REG_DPU_EW_OP_VALUE_1					0x00004094
#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK			0xffffffff
#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT			0
#define REG_DPU_EW_OP_VALUE_2					0x00004098
#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK			0xffffffff
#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT			0
#define REG_DPU_EW_OP_VALUE_3					0x0000409c
#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK			0xffffffff
#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT			0
#define REG_DPU_EW_OP_VALUE_4					0x000040a0
#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK			0xffffffff
#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT			0
#define REG_DPU_EW_OP_VALUE_5					0x000040a4
#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK			0xffffffff
#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT			0
#define REG_DPU_EW_OP_VALUE_6					0x000040a8
#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK			0xffffffff
#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT			0
#define REG_DPU_EW_OP_VALUE_7					0x000040ac
#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK			0xffffffff
#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT			0
#define REG_DPU_SURFACE_ADD					0x000040c0
#define DPU_SURFACE_ADD_SURF_ADD__MASK				0xfffffff0
#define DPU_SURFACE_ADD_SURF_ADD__SHIFT				4
#define DPU_SURFACE_ADD_RESERVED_0__MASK			0x0000000f
#define DPU_SURFACE_ADD_RESERVED_0__SHIFT			0
#define REG_DPU_LUT_ACCESS_CFG					0x00004100
#define DPU_LUT_ACCESS_CFG_RESERVED_0__MASK			0xfffc0000
#define DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT			18
#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK		0x00020000
#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT		17
#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK			0x00010000
#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT			16
#define DPU_LUT_ACCESS_CFG_RESERVED_1__MASK			0x0000fc00
#define DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT			10
#define DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK			0x000003ff
#define DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT			0
#define REG_DPU_LUT_ACCESS_DATA					0x00004104
#define DPU_LUT_ACCESS_DATA_RESERVED_0__MASK			0xffff0000
#define DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT			16
#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK		0x0000ffff
#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT		0
#define REG_DPU_LUT_CFG						0x00004108
#define DPU_LUT_CFG_RESERVED_0__MASK				0xffffff00
#define DPU_LUT_CFG_RESERVED_0__SHIFT				8
#define DPU_LUT_CFG_LUT_CAL_SEL__MASK				0x00000080
#define DPU_LUT_CFG_LUT_CAL_SEL__SHIFT				7
#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK			0x00000040
#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT			6
#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK			0x00000020
#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT			5
#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK			0x00000010
#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT			4
#define DPU_LUT_CFG_LUT_LO_LE_MUX__MASK				0x0000000c
#define DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT			2
#define DPU_LUT_CFG_LUT_EXPAND_EN__MASK				0x00000002
#define DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT			1
#define DPU_LUT_CFG_LUT_ROAD_SEL__MASK				0x00000001
#define DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT				0
#define REG_DPU_LUT_INFO					0x0000410c
#define DPU_LUT_INFO_RESERVED_0__MASK				0xff000000
#define DPU_LUT_INFO_RESERVED_0__SHIFT				24
#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK			0x00ff0000
#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT			16
#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK			0x0000ff00
#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT			8
#define DPU_LUT_INFO_RESERVED_1__MASK				0x000000ff
#define DPU_LUT_INFO_RESERVED_1__SHIFT				0
#define REG_DPU_LUT_LE_START					0x00004110
#define DPU_LUT_LE_START_LUT_LE_START__MASK			0xffffffff
#define DPU_LUT_LE_START_LUT_LE_START__SHIFT			0
#define REG_DPU_LUT_LE_END					0x00004114
#define DPU_LUT_LE_END_LUT_LE_END__MASK				0xffffffff
#define DPU_LUT_LE_END_LUT_LE_END__SHIFT			0
#define REG_DPU_LUT_LO_START					0x00004118
#define DPU_LUT_LO_START_LUT_LO_START__MASK			0xffffffff
#define DPU_LUT_LO_START_LUT_LO_START__SHIFT			0
#define REG_DPU_LUT_LO_END					0x0000411c
#define DPU_LUT_LO_END_LUT_LO_END__MASK				0xffffffff
#define DPU_LUT_LO_END_LUT_LO_END__SHIFT			0
#define REG_DPU_LUT_LE_SLOPE_SCALE				0x00004120
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK	0xffff0000
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT	16
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK	0x0000ffff
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT	0
#define REG_DPU_LUT_LE_SLOPE_SHIFT				0x00004124
#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK			0xfffffc00
#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT		10
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK	0x000003e0
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT	5
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK	0x0000001f
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT	0
#define REG_DPU_LUT_LO_SLOPE_SCALE				0x00004128
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK	0xffff0000
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT	16
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK	0x0000ffff
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT	0
#define REG_DPU_LUT_LO_SLOPE_SHIFT				0x0000412c
#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK			0xfffffc00
#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT		10
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK	0x000003e0
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT	5
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK	0x0000001f
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT	0
#define REG_DPU_RDMA_RDMA_S_STATUS				0x00005000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK			0xfffc0000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT		18
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK			0x00030000
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT			16
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK			0x0000fffc
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT		2
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK			0x00000003
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT			0
#define REG_DPU_RDMA_RDMA_S_POINTER				0x00005004
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK		0xfffe0000
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT		17
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK			0x00010000
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT			16
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK		0x0000ffc0
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT		6
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK		0x00000020
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT	5
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK		0x00000010
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT		4
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK		0x00000008
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT		3
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK		0x00000004
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT		2
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK		0x00000002
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT		1
#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK			0x00000001
#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT			0
#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE			0x00005008
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK		0xfffffffe
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT	1
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK		0x00000001
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT		0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH			0x0000500c
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK		0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT		13
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK		0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT		0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT			0x00005010
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK		0xe0000000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT	29
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK	0x1fff0000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT	16
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK		0x0000e000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT	13
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK		0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT		0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL			0x00005014
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK	0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT	13
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK		0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT		0
#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR				0x00005018
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT	0
#define REG_DPU_RDMA_RDMA_BRDMA_CFG				0x0000501c
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK		0xffffffe0
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT		5
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK		0x0000001e
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT		1
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK		0x00000001
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT		0
#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR				0x00005020
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT		0
#define REG_DPU_RDMA_RDMA_NRDMA_CFG				0x00005028
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK		0xffffffe0
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT		5
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK		0x0000001e
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT		1
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK		0x00000001
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT		0
#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR				0x0000502c
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT		0
#define REG_DPU_RDMA_RDMA_ERDMA_CFG				0x00005034
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK		0xc0000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT		30
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK		0x20000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT		29
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK		0x10000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT		28
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK		0x0ffffff0
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT		4
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK		0x0000000c
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT		2
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK		0x00000002
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT		1
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK		0x00000001
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT		0
#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR				0x00005038
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK		0xffffffff
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT		0
#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE			0x00005040
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK	0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT	4
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK		0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT		0
#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG			0x00005044
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK		0xfffc0000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT	18
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK	0x00038000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT	15
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK		0x00007800
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT		11
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK		0x00000700
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT		8
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK	0x000000e0
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT	5
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK	0x00000010
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT	4
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK	0x00000008
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT	3
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK		0x00000006
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT		1
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK	0x00000001
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT	0
#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG				0x00005048
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK		0xfff80000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT	19
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK		0x0007c000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT		14
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK		0x00002000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT		13
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK		0x00001000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT		12
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK	0x00000e00
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT	9
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK	0x000001c0
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT	6
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK		0x00000038
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT		3
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK		0x00000007
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT		0
#define REG_DPU_RDMA_RDMA_SURF_NOTCH				0x0000504c
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK		0xfffffff0
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT		4
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT		0
#define REG_DPU_RDMA_RDMA_PAD_CFG				0x00005064
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK			0xffff0000
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT			16
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK			0x0000ff80
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT			7
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK			0x00000070
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT			4
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK			0x00000008
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT			3
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK			0x00000007
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT			0
#define REG_DPU_RDMA_RDMA_WEIGHT				0x00005068
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK			0xff000000
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT			24
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK			0x00ff0000
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT			16
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK			0x0000ff00
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT			8
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK			0x000000ff
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT			0
#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH				0x0000506c
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK		0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT	4
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK		0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT		0

// ===== MESA CORE+DPU+PC EMIT (rest of fill_first_regcmd) =====
   EMIT(REG_CORE_MISC_CFG, misc_cfg);
   EMIT(REG_CORE_DATAOUT_SIZE_0,
        CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT(task->output_height - 1) |
           CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH(task->output_width - 1));
   EMIT(REG_CORE_DATAOUT_SIZE_1,
        CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL(task->output_channels - 1));
   EMIT(REG_CORE_CLIP_TRUNCATE,
        CORE_CLIP_TRUNCATE_CLIP_TRUNCATE(operation->truncate_bits));
   emit_raw(regs, CORE | 0x1, 0x3030, 0);

   uint32_t feat_mode_cfg =
      DPU_FEATURE_MODE_CFG_BURST_LEN(15) | DPU_FEATURE_MODE_CFG_OUTPUT_MODE(2);
   if (operation->depthwise)
      feat_mode_cfg |= DPU_FEATURE_MODE_CFG_CONV_MODE(3);

   EMIT(REG_DPU_FEATURE_MODE_CFG, feat_mode_cfg);
   EMIT(REG_DPU_DATA_FORMAT, 0);
   EMIT(REG_DPU_OFFSET_PEND, 0);
   EMIT(REG_DPU_DST_BASE_ADDR,
        rkt_get_tensor(subgraph, operation->output_index)->phys_addr +
           task->output_offset);
   EMIT(REG_DPU_DST_SURF_STRIDE,
        DPU_DST_SURF_STRIDE_DST_SURF_STRIDE(task->output_surface_stride));
   EMIT(REG_DPU_DATA_CUBE_WIDTH,
        DPU_DATA_CUBE_WIDTH_WIDTH(task->output_width - 1));
   EMIT(REG_DPU_DATA_CUBE_HEIGHT,
        DPU_DATA_CUBE_HEIGHT_HEIGHT(task->output_height - 1));
   EMIT(REG_DPU_DATA_CUBE_NOTCH_ADDR, 0);
   EMIT(REG_DPU_DATA_CUBE_CHANNEL,
        DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL(task->output_channels_real - 1) |
           DPU_DATA_CUBE_CHANNEL_CHANNEL(task->output_channels - 1));
   EMIT(REG_DPU_BS_CFG, DPU_BS_CFG_BS_ALU_ALGO(2) | DPU_BS_CFG_BS_ALU_SRC(1) |
                           DPU_BS_CFG_BS_RELU_BYPASS(1) |
                           DPU_BS_CFG_BS_MUL_BYPASS(1));
   EMIT(REG_DPU_BS_ALU_CFG, 0);
   EMIT(REG_DPU_BS_MUL_CFG, 0);
   EMIT(REG_DPU_BS_RELUX_CMP_VALUE, 0);

   if (operation->depthwise) {
      EMIT(REG_DPU_BS_OW_CFG, DPU_BS_OW_CFG_SIZE_E_2(3) |
                                 DPU_BS_OW_CFG_SIZE_E_1(3) |
                                 DPU_BS_OW_CFG_SIZE_E_0(3));
   } else {
      EMIT(REG_DPU_BS_OW_CFG, DPU_BS_OW_CFG_SIZE_E_2(1) |
                                 DPU_BS_OW_CFG_SIZE_E_1(1) |
                                 DPU_BS_OW_CFG_SIZE_E_0(1));
   }

   EMIT(REG_DPU_BS_OW_OP, DPU_BS_OW_OP_OW_OP(0x80 - weights_zero_point));

   EMIT(REG_DPU_WDMA_SIZE_0,
        DPU_WDMA_SIZE_0_CHANNEL_WDMA(task->output_channels - 1));
   EMIT(REG_DPU_WDMA_SIZE_1,
        DPU_WDMA_SIZE_1_HEIGHT_WDMA(task->output_height - 1) |
           DPU_WDMA_SIZE_1_WIDTH_WDMA(task->output_width - 1));
   EMIT(REG_DPU_BN_CFG,
        DPU_BN_CFG_BN_RELU_BYPASS(1) | DPU_BN_CFG_BN_MUL_BYPASS(1) |
           DPU_BN_CFG_BN_ALU_BYPASS(1) | DPU_BN_CFG_BN_BYPASS(1));
   EMIT(REG_DPU_BN_ALU_CFG, 0);
   EMIT(REG_DPU_BN_MUL_CFG, 0);
   EMIT(REG_DPU_BN_RELUX_CMP_VALUE, 0);

   if (operation->add_tensor != -1) {
      EMIT(REG_DPU_EW_CFG,
           DPU_EW_CFG_EW_CVT_TYPE(1) | DPU_EW_CFG_EW_DATA_MODE(1) |
              DPU_EW_CFG_EDATA_SIZE(1) | DPU_EW_CFG_EW_ALU_ALGO(2) |
              DPU_EW_CFG_EW_RELU_BYPASS(1) | DPU_EW_CFG_EW_LUT_BYPASS(1) |
              DPU_EW_CFG_EW_OP_SRC(1));

      /* See http://nvdla.org/hw/v1/ias/precision.html#element-wise */
      EMIT(REG_DPU_EW_CVT_OFFSET_VALUE, operation->addition_offset);

      float add_scale =
         operation->addition_scale / (task->input_scale * task->weights_scale);

      uint32_t add_scale_bits = fui(add_scale);
      /* Taken from
       * https://github.com/pytorch/QNNPACK/blob/master/src/qnnpack/requantization.h#L130
       */
      unsigned add_shift = 127 + 31 - 32 - (add_scale_bits >> 23) + 16;

      unsigned scale = ((add_scale_bits >> 9) & 0x7fff);
      if (scale < 1 << 14)
         scale |= 1 << 14;

      EMIT(REG_DPU_EW_CVT_SCALE_VALUE,
           DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT(add_shift - 1) |
              DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE(scale));

      EMIT(REG_DPU_EW_RELUX_CMP_VALUE, 0x0);

      float out_conv_scale =
         (task->input_scale * task->weights_scale) / task->output_scale;
      uint32_t out_scale_bits = fui(out_conv_scale);
      unsigned out_shift = 127 + 31 - 32 - (out_scale_bits >> 23) + 16;
      if (operation->truncate_bits > 0)
         out_shift--;
      unsigned out_scale = ((out_scale_bits >> 9) & 0x7fff) + 1;
      if (out_scale < 1 << 14)
         out_scale |= 1 << 14;

      EMIT(REG_DPU_OUT_CVT_OFFSET, offset);
      EMIT(REG_DPU_OUT_CVT_SCALE, DPU_OUT_CVT_SCALE_OUT_CVT_SCALE(out_scale));
      EMIT(REG_DPU_OUT_CVT_SHIFT, DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT(out_shift - 1));
   } else {
      EMIT(REG_DPU_EW_CFG,
           DPU_EW_CFG_EW_RELU_BYPASS(1) | DPU_EW_CFG_EW_OP_CVT_BYPASS(1) |
              DPU_EW_CFG_EW_LUT_BYPASS(1) | DPU_EW_CFG_EW_OP_BYPASS(1) |
              DPU_EW_CFG_EW_BYPASS(1));
      EMIT(REG_DPU_EW_CVT_OFFSET_VALUE, 0);
      EMIT(REG_DPU_EW_CVT_SCALE_VALUE, DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE(1));
      EMIT(REG_DPU_EW_RELUX_CMP_VALUE, 0);
      EMIT(REG_DPU_OUT_CVT_OFFSET, offset);

      float conv_scale =
         (task->input_scale * task->weights_scale) / task->output_scale;
      // DBG("conv_scale %f\n", conv_scale);
      uint32_t scale_bits = fui(conv_scale);
      /* Taken from
       * https://github.com/pytorch/QNNPACK/blob/master/src/qnnpack/requantization.h#L130
       */
      unsigned shift = 127 + 31 - 32 - (scale_bits >> 23) + 16;

      if (operation->truncate_bits > 0)
         shift--;

      unsigned scale = ((scale_bits >> 9) & 0x7fff) + 1;
      if (scale < 1 << 14)
         scale |= 1 << 14;

      EMIT(REG_DPU_OUT_CVT_SCALE, DPU_OUT_CVT_SCALE_OUT_CVT_SCALE(scale));
      EMIT(REG_DPU_OUT_CVT_SHIFT, DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT(shift - 1));
   }

   EMIT(REG_DPU_EW_OP_VALUE_0, 0);
   EMIT(REG_DPU_EW_OP_VALUE_1, 0);
   EMIT(REG_DPU_EW_OP_VALUE_2, 0);
   EMIT(REG_DPU_EW_OP_VALUE_3, 0);
   EMIT(REG_DPU_EW_OP_VALUE_4, 0);
   EMIT(REG_DPU_EW_OP_VALUE_5, 0);
   EMIT(REG_DPU_EW_OP_VALUE_6, 0);
   EMIT(REG_DPU_EW_OP_VALUE_7, 0);
   EMIT(REG_DPU_SURFACE_ADD, DPU_SURFACE_ADD_SURF_ADD(task->surfaces_per_row));
   emit_raw(regs, DPU | 0x1, 0x40c4, 0);
   EMIT(REG_DPU_LUT_ACCESS_CFG, 0);
   EMIT(REG_DPU_LUT_ACCESS_DATA, 0);
   EMIT(REG_DPU_LUT_CFG, 0);
   EMIT(REG_DPU_LUT_INFO, 0);
   EMIT(REG_DPU_LUT_LE_START, 0);
   EMIT(REG_DPU_LUT_LE_END, 0);
   EMIT(REG_DPU_LUT_LO_START, 0);
   EMIT(REG_DPU_LUT_LO_END, 0);
   EMIT(REG_DPU_LUT_LE_SLOPE_SCALE, 0);
   EMIT(REG_DPU_LUT_LE_SLOPE_SHIFT, 0);
   EMIT(REG_DPU_LUT_LO_SLOPE_SCALE, 0);
   EMIT(REG_DPU_LUT_LO_SLOPE_SHIFT, 0);
   EMIT(REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH,
        DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH(task->output_width - 1));
   EMIT(REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT,
        DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT(task->output_height - 1));
   EMIT(REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL,
        DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL(task->output_channels - 1));

   if (operation->add_tensor != -1) {
      EMIT(REG_DPU_RDMA_RDMA_SRC_BASE_ADDR,
           rkt_get_tensor(subgraph, operation->add_tensor)->phys_addr +
              task->output_offset);
   } else {
      EMIT(REG_DPU_RDMA_RDMA_SRC_BASE_ADDR, 0);
   }

   EMIT(REG_DPU_RDMA_RDMA_BRDMA_CFG, DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE(1));
   EMIT(REG_DPU_RDMA_RDMA_BS_BASE_ADDR,
        rkt_resource(operation->biases)->phys_addr);
   EMIT(REG_DPU_RDMA_RDMA_NRDMA_CFG, 0);
   EMIT(REG_DPU_RDMA_RDMA_BN_BASE_ADDR, 0);

   unsigned ew_stride =
      MAX2(operation->output_width * operation->output_height, 12);

   if (operation->add_tensor != -1) {
      EMIT(REG_DPU_RDMA_RDMA_ERDMA_CFG,
           DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE(1) |
              DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE(1));
      unsigned ew_base_offset =
         operation->output_width * operation->output_height * ATOMIC_K_SIZE;
      EMIT(REG_DPU_RDMA_RDMA_EW_BASE_ADDR,
           rkt_get_tensor(subgraph, operation->add_tensor)->phys_addr +
              task->output_offset + ew_base_offset);
      EMIT(REG_DPU_RDMA_RDMA_EW_SURF_STRIDE,
           DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE(ew_stride));
   } else {
      EMIT(REG_DPU_RDMA_RDMA_ERDMA_CFG, DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE(1));
      EMIT(REG_DPU_RDMA_RDMA_EW_BASE_ADDR, 0);
      EMIT(REG_DPU_RDMA_RDMA_EW_SURF_STRIDE, 0);
   }

   uint32_t rdma_feat_mode_cfg = 0x0;

   if (operation->add_tensor != -1) {
      rdma_feat_mode_cfg |= DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN(15) |
                            DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE(5);
   } else {
      rdma_feat_mode_cfg |= DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN(15) |
                            DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE(1);
   }

   if (operation->depthwise)
      rdma_feat_mode_cfg |= DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE(3);

   EMIT(REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG, rdma_feat_mode_cfg);
   EMIT(REG_DPU_RDMA_RDMA_SRC_DMA_CFG, 0);

   unsigned surf_notch =
      ew_stride +
      task->output_width * (operation->output_height - task->output_height);

   if (operation->input_width == 3) {
      surf_notch = 15;
   }

   if (operation->add_tensor != -1) {
      EMIT(REG_DPU_RDMA_RDMA_SURF_NOTCH,
           DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR(surf_notch));
   } else {
      EMIT(REG_DPU_RDMA_RDMA_SURF_NOTCH, 0);
   }

   EMIT(REG_DPU_RDMA_RDMA_PAD_CFG, 0);
   EMIT(REG_DPU_RDMA_RDMA_WEIGHT,
        DPU_RDMA_RDMA_WEIGHT_E_WEIGHT(1) | DPU_RDMA_RDMA_WEIGHT_N_WEIGHT(1) |
           DPU_RDMA_RDMA_WEIGHT_B_WEIGHT(1) | DPU_RDMA_RDMA_WEIGHT_M_WEIGHT(1));

   if (operation->add_tensor != -1) {
      EMIT(REG_DPU_RDMA_RDMA_EW_SURF_NOTCH,
           DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH(surf_notch));
   } else {
      EMIT(REG_DPU_RDMA_RDMA_EW_SURF_NOTCH, 0x0);
   }

   if (num_tasks == 1)
      util_dynarray_append_typed(regs, uint64_t, 0x0);
   else
      EMIT(REG_PC_BASE_ADDRESS, 0);

   EMIT(REG_PC_REGISTER_AMOUNTS, 0);

   /* TRM: before op_en, 64'h0041_xxxx_xxxx_xxxx must be set. */
   util_dynarray_append_typed(regs, uint64_t, 0x0041000000000000);

   /* TRM: 64'h0081_0000_007f_0008 will set each block's op_en(CNA, CORE, ...,
    * PPU_RDMA). */
   emit_raw(regs, 0x81, REG_PC_OPERATION_ENABLE,
            PC_OPERATION_ENABLE_RESERVED_0(14) | PC_OPERATION_ENABLE_OP_EN(1));
}

void
rkt_fill_regcmd(struct rkt_ml_subgraph *subgraph,
                const struct rkt_operation *operation,
                struct util_dynarray *regs, unsigned task_num)
{
   /*
    * TODO: We should only need to set all the registers on the regcmd for the first
    * task in an operation, but for now set them all to be sure.
    */
   fill_first_regcmd(subgraph, operation, regs, task_num);
}
