Pre-flight (5 steps): backup, pstore, serial console verify
Debug base kernel (8 steps): PROVE_LOCKING + LOCKDEP + DEBUG_*
full kernel rebuild, separate extlinux label, keep vanilla default
Bisect-apply (4 steps): 0004 → 0005 → 0006 → 0007, reboot+test between each
Risk register: 5 risks with mitigations
Total wall-time: ~150 min if clean
Pending Phase 5 architect review (Sonnet) before any execution.
Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
Markus Fritsche