Cycle 5 Phase 4: QPU CDEF shader plan (predicted deep RED)
Per-block stencil: 12 constrain ops per pixel, 64 pixels per block, 4 blocks/WG, 256 invocations/WG. Predicted R5 = 0.03 (deep RED) from cycle-3 MC scaling. Plan calls out 5 Phase 5 review items, notably sentinel handling and signed/unsigned min/max distinction. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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---
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cycle: 5
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phase: 4
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status: draft, awaiting Phase 5 review
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date_opened: 2026-05-18
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parent: k5_cdef_phase3.md
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predicted_R: 0.02-0.05 (deep RED)
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---
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# Cycle 5, Phase 4 — QPU CDEF shader plan
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Plan a Vulkan compute shader for the AV1 CDEF primary+secondary
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8×8 luma filter on V3D 7.1. Predicted **deep RED** (R₅ = 0.02-0.05);
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plan + build it anyway because:
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- Confirms the prediction with measured data (or refutes it).
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- Provides the dispatch path needed for Phase 8 V4L2 wrapper.
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- Closes cycle 5 (Phases 1-7 all on the record).
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## Kernel shape (NEON reference: 263 ns/block)
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Per 8×8 output block: 8 directions table, 2 offsets each. For
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each output pixel:
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- 2 primary taps (off1, -off1) using `dir`
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- 4 secondary taps (off2, -off2, off3, -off3) using `(dir+2)%8` and `(dir-2+8)%8`
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- For each of 2 k-rounds (different tap weights)
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- 12 `constrain()` ops per pixel × 64 pixels = **768 constrain ops per block**
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- Plus min/max bookkeeping for iclip
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The constrain math:
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```
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diff = p - px;
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adiff = abs(diff);
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clip = max(0, threshold - (adiff >> shift));
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constrained = sign(diff) * min(adiff, clip);
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sum += tap * constrained;
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```
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Output: `dst[r,c] = clamp(px + ((sum - (sum<0) + 8) >> 4), min, max);`
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## V3D substrate fit (phase0 constraints)
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- **No DP4A**: each constrain is scalar int math; no vector packing
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helps (per cycle 3 MC finding). Predicted instruction count
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proportional to ops.
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- **16KB shared**: not needed — each pixel computes independently;
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no row sharing in compute side (tmp is read-only input).
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- **subgroupSize=16**: 1 pixel per lane × 16 lanes/sg = 16 pixels
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per sg. Block of 64 pixels = 4 sg slots. Better: 2 blocks per
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WG of 256 invocations (16 sg) → 256 pixels = 4 blocks per WG.
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Following cycle-2 pattern: aim for **64 blocks/WG**? Too high
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— 64 × 64 = 4096 pixels/WG → 256 lanes × 16 pixels/lane.
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Wait — 256 lanes total, 1 pixel/lane → 256 pixels = 4 blocks/WG.
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Settle on **4 blocks/WG**, 256 invocations.
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- **≤8 SSBO**: need 3 (meta, tmp, dst). Comfortable.
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- **No shaderFloat16/Int8 ALU**: int math everywhere. uint8 dst
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via storageBuffer8BitAccess (cycle-1 v4 pattern).
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## SSBO layout
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- `Meta[i]`: `uvec4(dst_off_bytes, params0, params1, dir)` where
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`params0 = (pri | sec << 8 | damping << 16)` and
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`params1 = tmp_off_bytes` (offset to block-origin = padded_origin + 2*16+2)
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- `Tmp[]`: `uint16` array (`uint8_t` SSBO with manual 16-bit
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read? Or `storageBuffer16BitAccess`? V3D 7.1 supports the
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16-bit extension.)
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- `Dst[]`: `uint8_t` array
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Use 16-bit storage extension for tmp.
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## Lane decomposition
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256 invocations / WG, 4 blocks/WG:
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- `lane_in_wg = 0..255`
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- `block_in_wg = lane_in_wg / 64` (0..3)
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- `pixel_in_block = lane_in_wg & 63` (0..63 → row=>>3, col=&7)
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- `block_idx = wg_id * 4 + block_in_wg`
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No barrier needed; each pixel computes independently.
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## Push constants
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```glsl
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layout(push_constant) uniform PC {
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uint n_blocks;
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uint tmp_stride_u16; // = 16
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uint dst_stride_u8;
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uint _pad;
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} pc;
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```
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## Directions table
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Store the 14-entry stride-16 directions table as a `const uint
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dirs[14]` in the shader, packed as `(off1 << 16) | off2` per
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direction (both signed offsets fit in int16). Read via index.
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Alternative: store as constants array (compiler may unroll into
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uniform LUT). Same as cycle-2 LPF stored its tap weights.
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## Shader pseudo-code
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```glsl
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void main() {
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uint gid = gl_GlobalInvocationID.x;
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uint wg_id = gid / 256u;
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uint block_in_wg = (gid & 255u) >> 6; // 0..3
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uint px_idx = gid & 63u; // 0..63
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uint row = px_idx >> 3; // 0..7
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uint col = px_idx & 7u; // 0..7
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uint block_idx = wg_id * 4u + block_in_wg;
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if (block_idx >= pc.n_blocks) return;
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uvec4 m = u_meta.meta[block_idx];
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uint dst_off = m.x + row * pc.dst_stride_u8 + col;
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uint tmp_off = m.w + row * pc.tmp_stride_u16 + col; // m.w = tmp block-origin u16 offset
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int pri = int(m.y & 0xffu);
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int sec = int((m.y >> 8) & 0xffu);
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int damping = int((m.y >> 16) & 0xffu);
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int dir = int(m.z & 7u);
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int px = int(u_tmp.tmp[tmp_off]);
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int sum = 0;
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int mn = px, mx = px;
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int pri_shift = max(0, damping - ulog2(pri));
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int sec_shift = damping - ulog2(sec);
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// pri_tap[k] for k=0,1 = 4-(pri&1), then (tap & 3) | 2
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int pri_tap0 = 4 - (pri & 1);
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int pri_tap1 = (pri_tap0 & 3) | 2;
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int pri_idx = dir;
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int sec1_idx = (dir + 2) & 7;
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int sec2_idx = (dir + 6) & 7;
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// k=0
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{
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int off = dirs_off1[pri_idx];
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int p0 = int(u_tmp.tmp[tmp_off + off]);
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int p1 = int(u_tmp.tmp[tmp_off - off]);
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sum += pri_tap0 * constrain(p0 - px, pri, pri_shift);
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sum += pri_tap0 * constrain(p1 - px, pri, pri_shift);
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mn = min(min(mn, p0), p1); mx = max(max(mx, p0), p1);
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// ... 4 secondary taps the same way for off2, off3
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}
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// k=1: same with off2 versions
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int adj = (sum - int(sum < 0) + 8) >> 4;
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int out = clamp(px + adj, mn, mx);
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u_dst.dst[dst_off] = uint8_t(out);
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}
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```
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Note: dirs_off1/dirs_off2 are per-k-round offsets. For k=0 use
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`*[idx][0]` (the "+1 row" component); for k=1 use `*[idx][1]`
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(the "+2 rows" component).
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## Throughput prediction
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NEON 1-core: 3.81 Mblock/s = 262 ns/block.
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V3D 7.1 compute estimate (per cycle 3 MC pattern):
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- 12 constrain ops × 8 SMUL24+ADD per constrain = ~96 instructions per pixel
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- 64 pixels per block, 4 blocks/WG → 256 lanes work in parallel
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- Per-block QPU latency ≈ instruction count / lanes × cycle time
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- Predicted: ~5000-8000 ns per block → 0.125-0.2 Mblock/s
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- R₅ = 0.125 / 3.81 = **0.033** (deep RED, matches prediction)
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shaderdb prediction:
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- ~800-1200 instructions (similar shape to cycle 1 IDCT, more
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ops though)
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- 2-4 threads (if uniform count stays < 144 per phase5''' finding 2)
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- uniform count: 14 entries × 2 offsets = 28; + tap weights 4
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= small. Should stay well below threshold. Predict 4 threads.
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## Phase 5 review focus
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Particular review items for the Phase 5 second-model audit:
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1. **Sentinel handling**: when reading from tmp halo, raw uint16
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values could be 0x8000 (INT16_MIN sentinel from padding) for
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real picture-boundary blocks. Our cycle 5 bench uses random
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pixel values (no sentinels), but a production deployment would
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pass through padded blocks. The constrain() math naturally
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handles INT16_MIN-as-uint16=32768 (clip becomes 0), BUT the
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`min(mn, p)` should use UNSIGNED compare and `max(mx, p)`
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should use SIGNED compare to match NEON. GLSL's `min`/`max`
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on `int` is signed; need separate `umin` (or cast to uint).
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Concretely: `mn = int(min(uint(mn), uint(p)))`,
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`mx = max(mx, int(int16_t(p)))`.
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2. **OOB read on direction taps**: for blocks near the picture
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edge, the direction offsets reach into the halo. Our bench
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uses random pixels there (valid uint8). For deployment with
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sentinels, we need to either (a) zero-out halo values that are
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sentinels before reading or (b) accept the constrain-math-
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handles-it argument.
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3. **Tmp stride**: must equal 16 (stride_u16=16) to match the
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directions table that's baked at stride 16. push constant
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`tmp_stride_u16` should be const or asserted = 16 in bench.
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4. **dst_stride_u8**: cycle-2 LPF used dst_stride_u8 = 8 (for
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isolated blocks). Same here. Production deployment with real
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picture strides (e.g. 1920) would need re-validation.
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5. **Push-constant meta size**: m.z carries dir (only 3 bits used);
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could be packed into params0. But current layout simple, leave
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as-is.
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## Acceptance criteria
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- shaderdb predicted ≤ 1200 inst, ≥ 2 threads, ≤ 30 uniforms, no
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spills.
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- M1 bit-exact (use the same bench setup as Phase 3 but compare
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QPU output vs NEON output).
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- M2 captured (any number, even deep RED).
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- M4 measured against pure-NEON-4 baseline (expected: negative,
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per same-kernel pattern); cross-reference Issue 003 V1/V2 for
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the mixed-kernel context.
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## Estimated effort
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2-3 hours for the shader; 30 min for the M2 bench; 30 min for
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M4. Total: ~4 hours, then Phase 7 closure.
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