20e3d004ae
Per user direction at cycle-4 close: file wd=16 (trend prediction validation) and vertical variants (column-stride TMU behaviour unknown) as local issues for future cycles. Progress instead to CDEF (AV1) for codec breadth. docs/issues/001 — wd=16 prediction validation. Per cycle 4 lesson 4, trend says wd=16 likely flips M4 negative. Quick incremental cycle when revisited. docs/issues/002 — vertical variants. Different memory access pattern (column-strided vs row-strided). The load-bearing unknown is whether the cycle 2 +6.9% mixed gain survives the TMU coalescing shift. If positive, deployment recipe gains symmetry; if negative, must split by orientation. Both issues have acceptance criteria + expected outcomes documented. Cycle 5 next: CDEF (AV1) — codec-breadth expansion. No Gitea repo exists for daedalus-fourier yet (project is local- only). If a tracker is wanted, create the repo and migrate these .md files. For now they live in-tree as part of the project history. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
83 lines
3.2 KiB
Markdown
83 lines
3.2 KiB
Markdown
# Issue 002 — VP9 LPF vertical variants (v_4_8 / v_8_8)
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**Status**: open, not blocking
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**Type**: kernel-cycle (cycle 5/6 candidate)
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**Predicted verdict**: similar to horizontal cousins (k2/k4 = YELLOW PASS)
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**Priority**: low (different memory pattern; completeness)
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**Filed**: 2026-05-18
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## Background
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Cycles 2 and 4 implemented the **horizontal-direction** LPF inner
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filters (`h_4_8`, `h_8_8`). The corresponding **vertical-direction**
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filters (`v_4_8`, `v_8_8`) have the same arithmetic but a different
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memory access pattern: column-strided reads of 8 pixels (one per row)
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vs row-strided reads of 8 pixels (one per column).
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Concretely from `vp9dsp_template.c`:
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- `h_*_*_neon`: stridea=stride, strideb=1 (advance rows, neighborhood in cols)
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- `v_*_*_neon`: stridea=1, strideb=stride (advance cols, neighborhood in rows)
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The vertical variant tests whether the QPU's "8 lanes per row,
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contiguous read" assumption (cycles 2/4 wd=4/wd=8) generalises to
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the strided memory pattern. The TMU's coalescing behaviour may
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differ significantly when 8 lanes need to load from 8 different
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rows of the same column (cache-line-miss-y) vs 8 different cols of
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the same row (sequential).
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## What to do
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Cycle 5 or 6 (after CDEF), one cycle per variant:
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1. **v_4_8** — vertical 4-tap inner, 8-pixel edge (vertical edge,
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filter spans rows above/below).
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2. Optional **v_8_8** — vertical 8-tap inner.
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Each cycle: same shape as cycle 2/4 but
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- C reference: same `loop_filter` function, instantiated via
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`lf_8_fn(v, 4, 1, stride)` (note: stridea + strideb swapped).
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- NEON: `ff_vp9_loop_filter_v_4_8_neon` (in vendored `vp9lpf_neon.S`).
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- QPU geometry: same 32-edges/WG, but per-edge memory access shape
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changes — lanes now span 8 rows (strided by stride) of one column.
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## Key question to answer
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**Does the QPU's mixed-mode +6.9 % win (cycle 2 wd=4 horizontal)
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hold for the vertical variant?** The TMU latency / cache behaviour
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on column-strided reads is the main unknown. If positive: deployment
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recipe gains v variants symmetrically. If negative: deployment
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recipe needs to split by orientation (h on QPU, v on CPU).
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## Expected outcome
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| Quantity | Predicted |
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|---|---|
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| M1 bit-exact | 100 % |
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| M3 NEON | similar to h (NEON handles both orientations well) |
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| M2 QPU isolation | possibly LOWER than h variant (TMU column reads less coalesced) |
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| R isolation | 0.30-0.45 (ORANGE) |
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| M4 mixed | UNKNOWN — this is the load-bearing experiment |
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## Acceptance criteria
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- v_4_8 cycle 1-7 complete with M4 measurement
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- Decision: "v variants → QPU same as h" OR "v variants → CPU only"
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- Deployment recipe updated
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- Optional: v_8_8 follow-on cycle if v_4_8 was positive
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## Why deferred
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- Out of cycle 4's compressed scope (cycle 4 was a focused
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wd=4 → wd=8 extension)
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- User-stated cycle 5 direction was CDEF (AV1 coverage), not VP9
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variant completeness
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## Related
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- `docs/k2_deblock_phase4.md §"3. Workgroup geometry"` discusses
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the 32-edges-per-WG mapping that needs revisiting for v variant
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- `external/ffmpeg-snapshot/libavcodec/aarch64/vp9lpf_neon.S` —
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NEON refs already vendored for both v_4_8 and v_8_8
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- `phase0.md §2` device profile — TMU read patterns relevant for
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the column-strided question
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