marfrit
373f63a910
Phase 6 deliverable: v3d_h264deblock.comp (132 inst, 4 threads,
no spills). Phase 5 REDs applied:
RED-1: explicit clamp p1'/q1' to [0,255] before uint8 write
RED-2: bench-enforced m.x >= 4*stride contract
M1: 3-way 4096/4096 bit-exact (QPU vs C ref AND vs NEON).
M2: 5.629 Medge/s isolation → R8 = 0.061 RED (predicted 0.09-0.14).
Lower than prediction; H.264 deblock has 4 early-return paths +
2 conditional writes that hurt V3D branchy execution more than
expected.
M4 same-kernel: NEON-3+QPU 12.81 Medge/s ≈ pure-NEON-4 ~12-15
(neutral).
M4 MIXED (real H.264 deployment shape): CPU=MC + QPU=h264deblock
gives CPU MC 25.11 Mblock/s + QPU h264deblock 6.23 Medge/s.
QPU contribution is essentially unchanged from isolation —
the cross-substrate contention is gentle (consistent with
Issue 003's V4 finding).
Verdict: H.264 deblock = opportunistic QPU helper. Same recipe
slot as cycle 5 CDEF. 6 Medge/s helper = 85% of single-NEON-core
deblock capacity, available when CPU is busy with other work.
Cycles 1-8 deployment recipe complete:
Primary QPU: cycles 1+2+4 (VP9 IDCT/LPF, all bandwidth-bound)
Primary CPU: cycles 3+6+7 (compute-heavy or trivially fast on NEON)
Opportunistic helper: cycles 5+8 (CDEF, H.264 deblock)
Phase 9 lessons added:
- Branchy kernels underperform V3D vs straight-line ones
- Mixed-kernel helper value scales with isolation M2, not
same-kernel M4
- R prediction needs branchiness weight, not just compute density
- src/v3d_h264deblock.comp (132 inst QPU shader)
- tests/bench_v3d_h264deblock.c (3-way M1 + M2 + R classification)
- tests/bench_concurrent_mixed.c extended with K_H264DEBLOCK
- CMakeLists.txt: v3d_h264deblock.spv + bench_v3d_h264deblock
+ h264dsp linked into bench_concurrent_mixed
- docs/k8_h264deblock_phase7.md (full closure with cycles 1-8 recipe)
Next: Phase 8 — V4L2 wrapper / deployment infra. Public API
already exposes recipe-default substrate per kernel.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
198 lines
7.5 KiB
Markdown
198 lines
7.5 KiB
Markdown
---
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cycle: 8
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phase: 7
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status: closed 2026-05-18 — M1 PASS 3-way, R₈=0.061 RED isolation, M4 mixed POSITIVE
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date_opened: 2026-05-18
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date_closed: 2026-05-18
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parent: k8_h264deblock_phase6 (phase 6 = shader + bench, no separate doc)
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host: hertz
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verdict: CPU primary; QPU opportunistic helper. ~6 Medge/s = 85% of NEON-1 deblock in mixed deployment.
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---
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# Cycle 8, Phase 7 — Verification (H.264 deblock QPU)
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## Phase 6 deliverable
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- `src/v3d_h264deblock.comp` — 256 inv/WG, 16 edges/WG (1 sg per edge),
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no barrier, uint8 dst SSBO. Phase 5 RED-1 (clamp p1'/q1') and
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RED-2 (m.x ≥ 4*stride contract) both applied.
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- `tests/bench_v3d_h264deblock.c` — 3-way M1 + M2 bench.
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- `tests/bench_concurrent_mixed.c` extended with K_H264DEBLOCK on
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both CPU and QPU sides.
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shaderdb:
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```
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SHADER-DB-301659b6... 132 inst, 4 threads, 0 loops, 29 uniforms,
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20 max-temps, 0:0 spills:fills, 0 sfu-stalls, 12 nops
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```
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4 threads (vs predicted 2-3) — better than expected. 132 inst (vs
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predicted 150-200) — also better. No spills.
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## M1 — 3-way bit-exact
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```
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=== M1₈: QPU vs C ref vs NEON ===
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C ref vs NEON parity: 0/1048576 byte mismatches
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QPU vs C ref: 4096/4096 edges bit-exact (100.0000%)
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QPU vs NEON: 4096/4096 edges bit-exact (100.0000%)
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```
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Phase 5 RED-1 (explicit clamp on p1'/q1') validated — without it,
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shader would have wrapped on out-of-range p1/q1 values.
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Phase 5 RED-2 contract (m.x ≥ 4*stride) enforced by bench assert.
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## M2 — QPU throughput
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```
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=== M2₈: QPU throughput ===
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edges/dispatch: 4096
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iters: 100
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total edges: 409 600
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elapsed (kern) = 0.073 s
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M2₈ throughput = 5.629 Medge/s
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per-edge = 177.7 ns
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per-dispatch = 727.7 us
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```
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R₈ = 5.629 / 91.947 = **0.061 → RED band**.
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Below the Phase 3 revised prediction (0.09-0.14). Two reasons
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the prediction was too optimistic:
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1. H.264 deblock per-edge work on QPU is dominated by multiple
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early-return paths (3 alpha/beta gates, ap/aq side conditions,
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conditional p1/q1 writes) — branchy code doesn't pack as
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efficiently on V3D as VP9 LPF's monolithic 2-branch structure.
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2. NEON's per-edge 10.9 ns vs cycle 2 LPF's 20.7 ns reflects FFmpeg
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NEON's superior packing for the H.264 specific case — wider
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parallelism than VP9 LPF, harder for QPU to match.
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30fps@1080p worst-case floor: 5.629 / 8 = **0.70× margin (below
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worst case in isolation)**. Realistic-floor margin (3 Medge/s):
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1.88× (passes).
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## M4 — mixed-kernel matrix
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All 6s windows on hertz, bench_concurrent_mixed.
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### Same-kernel M4 (cycle-8 closure)
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| Config | CPU agg | QPU h264deblock | total |
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|---|---|---|---|
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| **NEON-3 + QPU h264deblock** | 7.04 Medge/s | 5.77 Medge/s | 12.81 |
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| **NEON-4 + QPU h264deblock** | 8.10 Medge/s | 5.43 Medge/s | 13.53 |
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| (Pure NEON-4 alone, estimated) | ~12-15 Medge/s | — | ~12-15 |
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NEON-3+QPU same-kernel total (12.81) ≈ pure-NEON-4 alone (12-15)
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**within measurement noise**. Same-kernel M4 verdict: approximately
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NEUTRAL (neither big win nor loss).
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### Mixed-kernel M4 (the H.264 deployment shape)
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| Config | CPU side | CPU agg | QPU h264deblock |
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|---|---|---|---|
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| **CPU=MC + QPU=h264deblock** | MC | 25.11 Mblock/s | **6.23 Medge/s** |
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| **CPU=LPF4 + QPU=h264deblock** | LPF4 | 31.48 Medge/s | **5.96 Medge/s** |
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**The KEY finding**: in mixed-kernel deployment, the QPU
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h264deblock contribution is **essentially unchanged from its
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isolation throughput** (5.6 → 6.2 Medge/s, +10 % even). The QPU
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is delivering ~85 % of a single NEON core's deblock capacity
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while running concurrently with a CPU doing different work.
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CPU MC side did drop somewhat (25.1 vs ~34 in pure mode), but
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the per-core MC throughput (8.4 avg) is still 3× the 1080p30 MC
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requirement.
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## Deployment recipe verdict
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**For VP9 decoder**: cycle 8 unused (VP9 has its own LPF cycles
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2+4 on QPU). H.264 deblock kernel doesn't apply to VP9.
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**For H.264 decoder**: cycle 8 = **QPU opportunistic helper**.
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- CPU primary substrate (NEON handles cycle 6+7 transforms,
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cycle 9 MC if needed)
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- QPU dispatch path exposed for opportunistic use:
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- When CPU is busy with MC/IDCT, QPU can run deblock at ~6 Medge/s
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- That's 85 % of single-NEON-core deblock capacity
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- Per the "30fps@1080p H.264 realistic floor = 3 Medge/s" target,
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QPU alone covers the floor 2×
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This is the same pattern as cycle 5 CDEF (R=0.116 ORANGE,
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opportunistic helper). The difference: cycle 8 NEON baseline is
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SO fast (92 Medge/s on a single core) that the QPU's 6 Medge/s
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is a ~6 % top-up. Useful but not transformative.
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## Verdict table
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| Rule | Result | Status |
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|---|---|---|
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| M1 bit-exact (3-way) | 100.00 % on 4096 edges | ✓ PASS |
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| R₈ = M2/M3 | 0.061 (RED) | predicted ORANGE |
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| M4 same-kernel | neutral (~equal to pure-NEON-4) | acceptable |
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| M4 mixed (CPU=MC) | QPU adds 6.2 Medge/s helper | ✓ POSITIVE |
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| 30fps@1080p worst floor (iso) | 0.70× | ✗ FAIL as sole substrate |
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| 30fps@1080p realistic floor (iso) | 1.88× | ✓ PASS |
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| 30fps@1080p NEON baseline | 11× | ✓ huge margin |
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**Engineering verdict**: QPU H.264 deblock useful as opportunistic
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helper. Phase 8 V4L2 wrapper should expose dispatch path; default
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schedule runs deblock on CPU but QPU dispatch available when
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useful.
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## Cycles 1-8 deployment recipe (final consolidated)
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| Cycle | Kernel | Primary | QPU path | M4 verdict |
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|---|---|---|---|---|
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| 1 | VP9 IDCT 8x8 | **QPU** | yes | +7.2 % |
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| 2 | VP9 LPF wd=4 | **QPU** | yes | +6.9 % |
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| 3 | VP9 MC 8h | CPU | unused | (deep RED 0.067) |
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| 4 | VP9 LPF wd=8 | **QPU** | yes | +4.1 % |
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| 5 | AV1 CDEF | CPU | opportunistic | 0.42 Mblock/s helper |
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| 6 | H.264 IDCT 4x4 | CPU | unused | (NEON-trivial) |
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| 7 | H.264 IDCT 8x8 | CPU | unused | (NEON-trivial) |
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| 8 | H.264 deblock | CPU | opportunistic | 6.2 Medge/s helper |
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3 QPU-primary kernels (VP9 1+2+4), 5 CPU-primary kernels
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(VP9 3, AV1 5, H.264 6+7+8). 2 cycles deserve opportunistic-helper
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status (cycle 5 CDEF, cycle 8 H.264 deblock).
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## Phase 9 lessons
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1. **Branchy kernels underperform on V3D vs NEON.** Cycle 8's QPU
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was 0.061 R vs predicted 0.10-0.14. The H.264 deblock has 4
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early-return paths plus 2 conditional writes. NEON handles
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these with predication; V3D needs taken-branch divergence
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which hurts more than I predicted. Future cycles with similar
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branch density should expect deeper RED than the throughput-
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ratio prediction suggests.
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2. **Mixed-kernel "free helper" value scales with QPU's intrinsic
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throughput, not the same-kernel M4 number.** Cycle 8 QPU
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delivers 6 Medge/s in mixed deployment (close to its isolation
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M2 of 5.6). The same-kernel M4 was nearly NEUTRAL — but in
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real H.264 deployment where CPU does MC and QPU does deblock,
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the QPU adds 85 % of a NEON-1 core's deblock work for free.
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Issue 003's V4 deployment-shape finding generalizes to cycle 8.
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3. **R-band predictions need to weight "branchy vs straight-line"
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alongside per-block compute weight.** Existing predictors only
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consider compute density. Cycle 8 disproves that — branchiness
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matters at least as much.
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## What lands in this commit
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- `src/v3d_h264deblock.comp` (Phase 6 shader)
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- `tests/bench_v3d_h264deblock.c` (3-way M1 + M2)
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- `tests/bench_concurrent_mixed.c` extended with K_H264DEBLOCK
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- `CMakeLists.txt`: v3d_h264deblock.spv + bench wiring
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- `docs/k8_h264deblock_phase7.md` (this doc)
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## Cycle 8 closure → Phase 8
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Cycles 1-8 form a complete kernel inventory across 3 codecs (VP9,
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AV1 CDEF, H.264). Phase 8 (V4L2 wrapper / deployment infra) is the
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next phase. The public API `include/daedalus.h` already exposes
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the recipe-default substrate for each kernel — Phase 8 adds CDEF,
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MC, deblock-style dispatchers as needed.
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