marfrit
356e446a49
Third daedalus-fourier kernel — VP9 8-tap regular subpel filter,
horizontal direction, 8-wide output. Multiply-heavy by design to
stress V3D's no-DP4A deficit. Full cycle Phase 1-7 + M4'''.
Phase 5''' second-model review delivered cleanly — caught 1 RED
bug pre-implementation (src_off off-by-3 indexing convention) and
2 YELLOW gaps (assert MUST language, shaderdb filter-LUT gate).
Without the review, M1''' would have failed silently on first run
with cryptic "high-index source pixels wrong" symptoms.
Phase 6 v1 first-light: M1''' 100.0000% bit-exact (65536/65536
blocks across all 16 mx phases). Phase 5''' filter-LUT prediction
materialised exactly: 197 uniforms (gate was 144), 2 threads (down
from cycle-2's 4 due to register pressure).
Performance:
M2''' = 1.413 Mblock/s (707.9 ns/block)
M3''' = 20.997 Mblock/s (NEON baseline phase3)
R''' = 0.067 (RED band — structural mismatch)
shaderdb: 488 inst, 2 threads, 197 uniforms, 25 max-temps, 0 spills
M4''' concurrent matrix (8s windows):
NEON 1-core 14.479 Mblock/s
NEON 4-core 15.248 Mblock/s <- baseline (compute-bound,
not bandwidth-saturated
like cycles 1+2!)
QPU only 1.380 Mblock/s
MIXED NEON-3 + QPU 12.277 Mblock/s <- -19.5% (FAIL gate)
MIXED NEON-4 + QPU 12.158 Mblock/s <- -20.3%
NEW cross-cycle finding (Phase 9 lesson 2): compute-bound CPU
workloads make the QPU-offload story collapse. Cycles 1+2 were
bandwidth-saturated (4-core scaling 0.56-0.82x of 1-core), so
freeing a CPU core via QPU offload added throughput. Cycle 3 MC
is compute-bound (4-core scaling 1.05x of 1-core — near-linear),
no free cycles to free. QPU contribution (0.45 Mblock/s in
contention) doesn't compensate for losing 1 NEON core delivering
~3.8 Mblock/s.
But 30fps@1080p floor: PASS in every config (1.4x to 15.7x
isolation margin). Per project_30fps_floor_is_fine.md, user-facing
test never fails — daily YouTube playback works fine on any CPU/QPU
split.
DEPLOYMENT RECIPE for higgs (cycle 3 confirmed split):
IDCT (k1) -> QPU (R=0.92, +7% mixed, frees CPU core)
LPF (k2) -> QPU (R=0.41, +7% mixed, frees CPU core)
MC (k3) -> CPU (R=0.067, -19.5% mixed — stays on CPU)
Entropy -> CPU (structurally serial)
Mixed-substrate deployment, not "QPU does everything". Realistic for
higgs: entropy + MC on 2-3 ARM cores; IDCT + LPF dispatched to QPU
concurrently; 1-2 ARM cores left for vscode etc.
New artifacts:
- src/v3d_mc_8h.comp — GLSL kernel
- tests/vp9_mc_ref.c — standalone C ref (REGULAR filter
embedded; clean transcription)
- tests/bench_neon_mc.c — M1'''_c + M3''' bench
- tests/bench_v3d_mc.c — M1''' + M2''' bench with contract
asserts + 30fps margin display
- tests/bench_concurrent_mc.c — M4''' pthread bench
- external/ffmpeg-snapshot/libavcodec/aarch64/vp9mc_neon.S (vendored)
- external/ffmpeg-snapshot/libavcodec/vp9_subpel_filters_table.c
(hand-extracted; provides
ff_vp9_subpel_filters symbol
without dragging in full vp9dsp.c)
- docs/k3_mc_phase{1,2,3,4,5,7}.md — full cycle documentation
Memory updates: project_30fps_floor_is_fine.md (user's 30fps target
recalibration), MEMORY.md index updated.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
73 lines
2.7 KiB
C
73 lines
2.7 KiB
C
/*
|
|
* Standalone bit-exact C reference for VP9 8-tap "regular" subpel
|
|
* filter, horizontal direction, 8-pixel-wide output. Transcribed
|
|
* from FFmpeg's libavcodec/vp9dsp_template.c FILTER_8TAP macro
|
|
* (vendored at external/ffmpeg-snapshot/). 8-bit pixels only.
|
|
*
|
|
* Filter coefficients embedded inline (REGULAR filter only, all 16
|
|
* subpel phases). Same values as ff_vp9_subpel_filters[1][mx] in
|
|
* external/ffmpeg-snapshot/libavcodec/vp9_subpel_filters_table.c.
|
|
*
|
|
* License: LGPL-2.1-or-later.
|
|
*
|
|
* Spec source: VP9 specification §8.5.1 — subpel motion compensation.
|
|
*/
|
|
#include <stdint.h>
|
|
#include <stddef.h>
|
|
|
|
static const int16_t vp9_8tap_regular_filters[16][8] = {
|
|
{ 0, 0, 0, 128, 0, 0, 0, 0 },
|
|
{ 0, 1, -5, 126, 8, -3, 1, 0 },
|
|
{ -1, 3, -10, 122, 18, -6, 2, 0 },
|
|
{ -1, 4, -13, 118, 27, -9, 3, -1 },
|
|
{ -1, 4, -16, 112, 37, -11, 4, -1 },
|
|
{ -1, 5, -18, 105, 48, -14, 4, -1 },
|
|
{ -1, 5, -19, 97, 58, -16, 5, -1 },
|
|
{ -1, 6, -19, 88, 68, -18, 5, -1 },
|
|
{ -1, 6, -19, 78, 78, -19, 6, -1 },
|
|
{ -1, 5, -18, 68, 88, -19, 6, -1 },
|
|
{ -1, 5, -16, 58, 97, -19, 5, -1 },
|
|
{ -1, 4, -14, 48, 105, -18, 5, -1 },
|
|
{ -1, 4, -11, 37, 112, -16, 4, -1 },
|
|
{ -1, 3, -9, 27, 118, -13, 4, -1 },
|
|
{ 0, 2, -6, 18, 122, -10, 3, -1 },
|
|
{ 0, 1, -3, 8, 126, -5, 1, 0 },
|
|
};
|
|
|
|
static inline uint8_t clip_u8(int x)
|
|
{
|
|
return (uint8_t)(x > 255 ? 255 : x < 0 ? 0 : x);
|
|
}
|
|
|
|
/*
|
|
* 8x8 horizontal 8-tap "put" (non-averaging). Width hard-coded 8.
|
|
* `src` must point at the row-0 output-column-0 source pixel; valid
|
|
* source memory must extend src[r*src_stride + (-3..+11)] for r=0..h-1.
|
|
* `dst` is written at dst[r*dst_stride + 0..7] for r=0..h-1.
|
|
*
|
|
* Matches ff_vp9_put_regular8_h_neon byte-for-byte on 8-bit input.
|
|
*/
|
|
void daedalus_vp9_put_regular_8h_ref(uint8_t *dst, ptrdiff_t dst_stride,
|
|
const uint8_t *src, ptrdiff_t src_stride,
|
|
int h, int mx, int my)
|
|
{
|
|
(void) my; /* horizontal-only filter ignores y phase */
|
|
const int16_t *F = vp9_8tap_regular_filters[mx & 15];
|
|
|
|
for (int r = 0; r < h; r++) {
|
|
for (int x = 0; x < 8; x++) {
|
|
int sum = F[0] * (int) src[x - 3]
|
|
+ F[1] * (int) src[x - 2]
|
|
+ F[2] * (int) src[x - 1]
|
|
+ F[3] * (int) src[x + 0]
|
|
+ F[4] * (int) src[x + 1]
|
|
+ F[5] * (int) src[x + 2]
|
|
+ F[6] * (int) src[x + 3]
|
|
+ F[7] * (int) src[x + 4];
|
|
dst[x] = clip_u8((sum + 64) >> 7);
|
|
}
|
|
dst += dst_stride;
|
|
src += src_stride;
|
|
}
|
|
}
|