marfrit
36eca40ff2
Phase 4 plan + Phase 5 second-model review (PASS-WITH-REVISIONS:
2 YELLOW contract gaps applied) + Phase 6 v1 implementation +
Phase 7 verification including M4'' concurrent gate.
Phase 5'' review delivered cleanly — no RED bugs (cycle 1 lessons
applied successfully). 2 YELLOW findings baked into phase4 §4:
- stride >= 4 contract added alongside m.x >= 4 (finding 2)
- assert(...) in bench made a MUST not a suggestion (finding 4)
- V3D divergence-cost note: don't restructure to always-execute,
masked lanes consume clock anyway (finding 3, informational)
Phase 6 v1 first-light hit M1'' 100.0000% bit-exact on first run
(65536/65536 edges) — the cycle-1 v4 patterns (WG=256, 2-per-sg,
uint8_t SSBO, oob early-return discipline) baked in from start
worked as expected.
Performance:
M2'' = 19.645 Medge/s (50.9 ns/edge)
M3'' = 48.285 Medge/s (NEON baseline from phase3)
R'' = 0.41 (ORANGE band - doesn't auto-close per
cycle-1 calibration adjustment)
shaderdb: 160 inst, **4 threads**, 0 spills, 21 max-temps —
shader is already at the compiler ceiling. No v2/v3/v4 iteration
loop like cycle 1 because there's nothing more to extract from
the compiled shape. The 30x gap between theoretical instruction
throughput and measured wall-clock is divergence-tax + memory
latency, not compile quality.
M4'' concurrent matrix on hertz (8s windows):
NEON-1 LPF 41.131 Medge/s
NEON-4 LPF 33.726 Medge/s <- realistic CPU ceiling
(per-core 7-9; same
bandwidth-saturation as
cycle-1 F1)
QPU only 14.299 Medge/s
MIXED NEON-3 + QPU 36.049 Medge/s <- +6.9% over NEON-4
MIXED NEON-4 + QPU 31.892 Medge/s <- -5.4% oversubscribed
The "freed-core" pattern generalizes from IDCT to LPF: NEON-3+QPU
beats pure NEON-4 by ~7% in both cycles. Cycle-2 NEW finding:
**oversubscribed mode hurts for lighter kernels** (LPF -5.4% vs
cycle-1 IDCT +9.4%). Recommendation for higgs deployment hardens
to "always N-1 NEON cores + QPU, never N + QPU".
Phase 9 lessons (in phase7 §"Phase 9 lessons"):
1. Cycle-1 v4-pattern is the v1 starting point (saves 3 iterations)
2. Phase 5 review pays off every cycle
3. R isolation misleading on bandwidth-saturated hardware
4. Oversubscription tax depends on kernel weight
5. shaderdb 4-threads/0-spills = compute not the bottleneck
New artifacts:
- src/v3d_lpf_h_4_8.comp — GLSL kernel
- tests/bench_v3d_lpf.c — M1'' + M2'' harness with
contract asserts + fm/hev
pass-rate instrumentation
- tests/bench_concurrent_lpf.c — M4'' pthread bench
(mirrors bench_concurrent.c)
- docs/k2_deblock_phase{4,5,7}.md — plan + review + verification
Project verdict: continue. Cycle 3 candidates: MC interpolation
(multiply-heavy, stress V3D SMUL24), CDEF (AV1-only, different
neighborhood shape), or wd=8/wd=16 LPF variants. User to direct.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
195 lines
7.6 KiB
Markdown
195 lines
7.6 KiB
Markdown
---
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cycle: 2
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phase: 7
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status: closed 2026-05-18 — PASS
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date_opened: 2026-05-18
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date_closed: 2026-05-18
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parent: k2_deblock_phase4.md (+ phase5 revisions)
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host: hertz (Pi 5, 8 GB, Debian Trixie, kernel 6.12.75+rpt-rpi-2712,
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Mesa 25.0.7-2+rpt4, V3D 7.1.7 @ 1 GHz, A76 @ 2.8 GHz)
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verdict: M4'' PASS — mixed +6.9 % over pure NEON-4; project continues
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---
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# Cycle 2, Phase 7 — Verification (v1 + M4'')
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Per `dev_process.md`: repeat measurements from Phase 3, compare
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explicitly to baseline. Phase 4 §6 predicted R'' ≈ 0.5–0.9 isolation,
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bandwidth ceiling at 0.87. Measured R'' = 0.41 isolation — below the
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predicted lower bound. Per cycle-1 calibration (M4 showed mixed >
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pure-CPU even at modest R), this triggers M4'' rather than honest-close.
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M4'' gate result: **PASS.** Project continues.
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## v1 first-light (single dispatch, isolation R'')
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```
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=== v3d LPF h_4_8 bench ===
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device: V3D 7.1.7.0
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n_edges: 65536 iters: 100
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fm pass rate: 8.09% (10k-edge sample)
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hev pass rate: 4.93% (of fm-passing)
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dispatch: 2048 WGs × 256 invocations = 65536 edges
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=== M1'': QPU vs C-reference bit-exact ===
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edges bit-exact: 65536 / 65536 (100.0000 %)
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total byte diffs: 0 / 4194304 (0.0000 %)
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=== M2'': QPU throughput ===
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M2'' throughput = 19.645 Medge/s
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per-edge = 50.9 ns
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per-dispatch = 3336.1 us
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R'' = M2''/M3'' = 0.407 → ORANGE band
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```
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shaderdb (v1 LPF kernel):
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```
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SHADER-DB-6c8e828054...: MESA_SHADER_COMPUTE shader:
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160 inst, 4 threads, 0 loops, 36 uniforms, 21 max-temps,
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0:0 spills:fills, 0 sfu-stalls, 160 inst-and-stalls, 15 nops
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```
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The shader is *already well-optimised by v3d_compiler*:
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- **4 hardware threads** (vs cycle-1 IDCT's 2 — better latency
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hiding from the start)
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- 0 spills:fills (compiler delivered)
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- 160 instructions — about 60 % of cycle-1 IDCT's 270
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Yet R'' = 0.41. The 30× gap between theoretical instruction
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throughput and measured wall-clock is **not** compile-quality
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limited. Plausible attribution:
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1. fm-pass rate 8 % → 92 % of edges read+compute then return.
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But masked lanes still pay clock (phase5'' finding 3) — no
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throughput benefit from early-return.
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2. Memory latency: per-edge 64 reads + 0-4 writes via TMU; less
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compute density per memory op than IDCT.
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3. v3dv per-dispatch overhead is 0.05 % of total at 3.3 ms
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per-dispatch — not the bottleneck.
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The fundamental issue: LPF on QPU is **memory-bound**, not
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compute-bound. Per-edge ~88 B of traffic × 19.6 Medge/s ≈
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1.7 GB/s — well below the 4 GB/s GPU bandwidth ceiling. The
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divergence tax may be eating the bandwidth headroom (lanes
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that early-return don't write but still consume cycle).
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## M4'' concurrent matrix (cycle-2 gate test)
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8-second time-based windows, hertz, all 65 536-edge dispatches:
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| Config | Medge/s | per-core (NEON) | vs NEON-4 |
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|---|---|---|---|
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| **NEON 1-core** | 41.131 | 41.131 | — |
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| **NEON 4-core** | 33.726 | 7.21 – 9.28 | **baseline ceiling** |
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| QPU alone (host on core 3) | 14.299 | n/a | — |
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| **MIXED NEON-3 + QPU** | **36.049** | 9.44 – 12.98 | **+6.9 %** |
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| MIXED NEON-4 + QPU (oversubscribed) | 31.892 | 6.45 – 8.02 | **−5.4 %** |
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**The gate verdict:** NEON-3 + QPU (36.05) **>** NEON-4 alone
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(33.73) by 2.32 Medge/s = +6.9 %. M4'' PASSES.
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QPU's contribution in mixed mode (4.0 Medge/s) is 28 % of its
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isolation throughput (14.3) — the same QPU-bandwidth-collapse
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under CPU contention seen in cycle-1 M4 (where QPU dropped from
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6.9 → 1.6 Medge/s = 23 % survival).
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## Cycle-2 vs cycle-1 M4 deltas
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| | Cycle 1 (IDCT) | Cycle 2 (LPF) |
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|---|---|---|
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| NEON 1-core (Mblock/s vs Medge/s) | 12.6 | 41.1 |
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| NEON 4-core | 7.07 | 33.7 |
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| QPU isolation | 6.89 | 14.3 |
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| R isolation (vs 1-core NEON) | 0.55 | 0.35 |
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| R isolation (vs 4-core NEON saturated) | 0.97 | 0.42 |
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| MIXED N3+Q vs N4 | **+7.2 %** | **+6.9 %** |
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| MIXED N4+Q vs N4 | +9.4 % (neutral-to-pos) | **−5.4 % (negative)** |
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The "freed-core" pattern generalizes: NEON-3+QPU > NEON-4 by
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roughly the same percentage in both cycles. The oversubscription
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flip (cycle 1 positive → cycle 2 negative) is the new finding:
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**lighter per-unit kernels are more sensitive to CPU/QPU-host
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contention**. For deployment on higgs the recommendation
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hardens to "always NEON-3 + QPU, never NEON-4 + QPU".
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## Phase 4''/5'' prediction calibration
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What Phase 4'' got right:
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- Bandwidth-bound — bench fm-pass rate confirms most edges don't
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even do the conditional write work, yet bandwidth is the
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ceiling
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- 4-thread shaderdb result — phase 4 §6 predicted "compute
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doesn't bottleneck"; confirmed
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What Phase 4'' got wrong:
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- Isolation R'' band 0.5–0.9 was too optimistic by ~25 %.
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Actual 0.41. Divergence tax was bigger than estimated.
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- Phase 5'' finding 3 specifically warned not to restructure
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for divergence — that holds; the 0.41 IS the floor.
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What this means: **the cycle-1-style "single big v4 jump from
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WG sweep" probably doesn't exist for LPF** — we're already at
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WG 256 from v1, already at 4 hardware threads, already at 0
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spills. The compiler delivered. The hardware limit on
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LPF-shape kernels appears to be ~14 Medge/s isolation. The
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project can pursue further optimization only by attacking the
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algorithm structure (e.g., fused multi-edge-per-WG with shared
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prefetch — but that adds shared mem and barriers, complicating
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divergence further).
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For now: cycle 2 closes as a YELLOW-PASS via M4''. Cycle 3 next.
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## Phase 7'' decision
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Per `k2_deblock_phase1.md §"Decision rules"` and cycle-1
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calibration adjustment:
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| Rule | Result | Status |
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|---|---|---|
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| M1'' bit-exact | 100.0000 % | ✓ PASS |
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| R'' = M2''/M3'' | 0.41 (ORANGE) | does not auto-close |
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| M4'' > pure-CPU 4-core | +6.9 % | ✓ PASS |
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| **Cycle verdict** | **YELLOW-via-M4''** | **continue to next kernel** |
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Phase 9 (lessons): see end of this doc.
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## Leaves open
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- **Real-bitstream fm-pass rate.** Bench's random distribution
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gives 8 % fm-pass. Real VP9 streams may be 30-60 %. If fm-pass
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rate matters for the divergence tax, real content might
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measurably shift M2''. Worth a sample-stream re-measurement
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if/when an end-to-end pipeline exists.
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- **Vertical variant v_4_8.** Different memory access pattern
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(column-strided reads). Cycle 2 v2 if there's a reason; not
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blocking.
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- **wd=8 and wd=16 filters.** Bigger conditional paths. Cycle 3+
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candidates.
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## Phase 9 lessons (added to project memory)
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1. **Cycle-1 v4-pattern is the v1 starting point.** Bake in WG 256,
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2-block-per-subgroup adaptation, uint8_t SSBO, oob early-return
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discipline, NO chained ternary from the start. Saves 3 iterations.
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2. **Phase 5 review pays off every cycle.** Cycle 1 caught 2 RED
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bugs; cycle 2 caught 2 YELLOW contract gaps (stride ≥ 4, assert
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discipline) and 1 V3D-specific divergence-cost warning. No
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wasted code from review-flagged bugs in either cycle.
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3. **R isolation is a misleading metric on bandwidth-saturated
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hardware.** Comparing QPU vs 1-core NEON is the wrong baseline
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when 4-core NEON only delivers 0.56-0.82× of 1-core scaled.
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The right comparison is QPU vs 4-core-NEON-saturated, then
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the mixed-vs-pure-CPU delta. Both cycles' M4 confirm this.
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4. **Oversubscription tax depends on kernel weight.** Heavy
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per-unit work (IDCT) tolerates NEON-4 + QPU (+9 %). Light
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per-unit work (LPF) is hurt by it (-5 %). Recommendation
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for deployment: always N-1 NEON cores + QPU, never N + QPU.
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5. **shaderdb at 4 threads / 0 spills means compute is not the
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bottleneck.** Subsequent optimization should target memory
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pattern (TMU prefetch, working-set tiling) or accept the
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silicon limit. Cycle 2 v1 hit this ceiling — no v2-v5
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iterations needed because there's nothing to improve in the
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compiled shader shape.
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