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8182e43c15
The YELLOW-band gate test from phase1.md (concurrent CPU+QPU vs
pure-CPU baseline). tests/bench_concurrent.c is a pthread harness
that runs N NEON workers (pinned to cores 0..N-1) and optionally a
QPU dispatch loop on its own pinned thread; 8s time-based windows;
sums per-worker block counts.
Raw results on hertz (1920x1088, 32640 blocks/dispatch):
Config Mblock/s 1080p FPS-eq
NEON 1-core 12.623 389.6
NEON 4-core 7.074 218.3 <- realistic CPU ceiling
QPU only 6.890 212.7
MIXED NEON-3 + QPU 7.583 234.0 <- +7.2 % over NEON-4
MIXED NEON-4 + QPU 7.739 238.9 <- +9.4 % oversubscribed
Headline findings beyond the gate test itself:
F1 — Pi 5 LPDDR4x saturates well before 4-core CPU scaling.
NEON-1 (12.6) > NEON-4 (7.1): 4 cores deliver 0.56x the
per-core throughput, not 4x. The realistic CPU ceiling for
memory-bound IDCT work is ~7 Mblock/s aggregate, not the
~32 Mblock/s a naive 4x scaling would predict. This recasts
phase7.md's R=0.92 framing: the right baseline is "4-core
NEON saturated", which the QPU effectively matches (6.89
vs 7.07) on its own.
F2 — QPU contributes meaningfully BECAUSE it doesn't fully share
the CPU's bandwidth bottleneck (own access channel + v3d L2
cache partially insulate it). Mixed adds the QPU's 0.51
Mblock/s on top of an already-saturated CPU.
F3 — Oversubscribed mode (NEON-4 + QPU) is not harmful — per-NEON
drops slightly but QPU adds more than the loss. Net +9 %.
F4 — Freed-core story is bigger than the throughput delta. In
mixed NEON-3+QPU, the 4th core is 100 % free for entropy
decode (Bool coder, ANS) which MUST run on CPU. Pure NEON-4
has nothing left. Realistic decode pipeline gets more like
a 30-50 % effective throughput uplift, not just 7 %.
Verdict per phase1.md YELLOW-band rule (mixed > pure-CPU): PASS.
Project continues to next-kernel cycle (recommend deblocking or
CDEF — same "small parallel block-level" workload class that
amortises the same M4 wins).
docs/phase7_M4.md captures the full M4 harness design, all 5
configs raw output, and the leaves-open items: M7 wall-power via
Himbeere plug, sustained-thermal test, realistic-bitstream
coefficient distribution, multi-frame async pipelining.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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7.7 KiB
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185 lines
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Markdown
---
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phase: 7 (M4 addendum)
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status: closed 2026-05-18
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date_opened: 2026-05-18
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date_closed: 2026-05-18
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parent: phase7.md
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host: hertz (Pi 5, 8 GB, Debian Trixie, kernel 6.12.75+rpt-rpi-2712, Mesa 25.0.7-2+rpt4, V3D 7.1.7 @ 1 GHz, A76 @ 2.8 GHz)
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verdict: GO — mixed CPU+QPU aggregate > pure 4-core NEON ceiling
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---
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# Phase 7 M4 — Concurrent CPU+QPU verification
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Per `phase1.md §"Decision rules"`, R = 0.92 from Phase 7 v4 lands
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in the YELLOW band (0.5 ≤ R < 1.0). The YELLOW rule says:
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> "QPU loses in isolation but is in the same order of magnitude.
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> *Concurrent-work hypothesis* becomes viable: at R ≈ 0.5 the QPU
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> can roughly handle half of decode while the CPU does the other
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> half + everything else. Add a Phase 1' measurement: M4 = combined
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> CPU+QPU throughput when both run concurrently (does total system
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> delivery exceed pure-CPU?). Then decide."
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M4 is that measurement. Verdict: **YES, mixed delivery exceeds the
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pure-CPU baseline. Project continues to next kernel.**
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## Harness
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`tests/bench_concurrent.c` — pthread workers (NEON), pthread QPU
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driver, time-based (not iteration-based) loop, pthread barrier for
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synchronised start, volatile flag for synchronised stop. Each NEON
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worker pinned to one core via `sched_setaffinity`; QPU host thread
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pinned to specified core. 8 second windows. Per-worker block counts
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summed at end.
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Bench modes:
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- `neon-only --threads N` — N NEON workers, no QPU
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- `qpu-only` — QPU dispatch loop on its own pthread, no NEON
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- `mixed --neon-threads N --qpu-core C` — both
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## Raw results (hertz, 1080p luma, 32 640 blocks/dispatch, 8s windows)
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```
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=== 1) NEON 1-core ===
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core 0: 12.623 Mblock/s (100 999 168 blocks / 8.001 s)
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AGGREGATE: 12.623 Mblock/s (= 389.6 1080p FPS-eq)
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=== 2) NEON 4-core ===
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core 0: 1.979 Mblock/s
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core 1: 1.585 Mblock/s
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core 2: 1.805 Mblock/s
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core 3: 1.706 Mblock/s
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AGGREGATE: 7.074 Mblock/s (= 218.3 1080p FPS-eq)
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=== 3) QPU only ===
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QPU (host on core 3): 6.890 Mblock/s
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AGGREGATE: 6.890 Mblock/s (= 212.7 1080p FPS-eq)
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=== 4) MIXED NEON-3 + QPU ===
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core 0: 2.049 Mblock/s
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core 1: 1.966 Mblock/s
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core 2: 1.968 Mblock/s
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QPU (host on core 3): 1.602 Mblock/s
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AGGREGATE: 7.583 Mblock/s (= 234.0 1080p FPS-eq)
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=== 5) MIXED NEON-4 + QPU (oversubscribed) ===
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core 1: 1.418 Mblock/s
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core 2: 1.300 Mblock/s
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core 3: 1.847 Mblock/s
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QPU (host on core 0): 1.725 Mblock/s
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AGGREGATE: 7.739 Mblock/s (= 238.9 1080p FPS-eq)
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```
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## Findings
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### Finding F1 — Pi 5 LPDDR4x bandwidth saturates well before 4-core CPU scaling
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This is the most important non-codec-specific result of the entire
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session. NEON 1-core delivers 12.6 Mblock/s; NEON 4-core delivers
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7.1 Mblock/s — **4 cores produce 0.56× the per-core throughput**,
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not 1× or 0.7×. The Pi 5's 17 GB/s LPDDR4x bus is genuinely the
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limit, not a Phase 0 hypothesis.
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This invalidates the implicit assumption from `phase0.md §6` that
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treated 4× single-core NEON as the relevant CPU ceiling. The real
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ceiling is **~7 Mblock/s aggregate, bandwidth-limited**, regardless
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of how many A76 cores you throw at it.
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For *any* memory-bound workload on this hardware: throwing more
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cores at it doesn't help. Going from 2 cores to 4 cores typically
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adds <30 % aggregate throughput, sometimes negative (cache eviction
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contention).
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### Finding F2 — QPU contributes meaningfully *because* it doesn't fully share the CPU's bandwidth bottleneck
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Per Phase 0 §2: "GPU sees 4–7 GB/s; CPU NEON gets 12–15 GB/s of
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the same 17 GB/s LPDDR4x." That framing suggested the QPU was
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*worse* on bandwidth. M4 inverts the conclusion: the QPU has its
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own access channel and L2 cache that partially insulate it from
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CPU contention. Mixed NEON-3 + QPU = 7.583 Mblock/s vs NEON-4 =
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7.074 — **the QPU adds 0.51 Mblock/s of incremental work** even
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when the CPU has saturated the bus. That's not 4 GB/s × QPU
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efficiency; it's the marginal contribution of an underutilised
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memory channel + GPU L2.
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### Finding F3 — Adding QPU on top of saturated NEON (oversubscribed) is *not* harmful
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NEON-4 + QPU = 7.739 > NEON-4 alone = 7.074 (+9.4 %). One might
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expect contention to drop CPU throughput by more than QPU adds,
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giving a net loss. It doesn't. Per-NEON-core in 4+QPU mode is
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~1.39-1.85 (vs 1.58-1.98 in NEON-4 alone) — small drop — and the
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QPU adds 1.725 to the total. Net win.
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### Finding F4 — The freed-core story is bigger than the throughput delta
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The straight delivery delta (NEON-3+QPU vs NEON-4) is only ~7 %.
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But the *qualitative* difference is that the 4th CPU core is
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completely free in mixed mode. For real codec work, entropy
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decode (VP9 Boolean coder, AV1 ANS coder) is structurally serial
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and *must* run on the CPU; the freed core handles it (plus
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browser logic, audio, the rest of the system). In pure 4-core
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NEON, every core is doing IDCT and there's nothing left for
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entropy. So the realistic comparison for an end-to-end
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decoder is **"3-core entropy + 1-core IDCT" vs "3-core entropy
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+ QPU IDCT"** — and the QPU-IDCT case wins by leaving entropy
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with 3 cores while still completing decode.
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## Decision per Phase 1 rules
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| Rule | Threshold | Measured | Verdict |
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|---|---|---|---|
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| Phase 1 §"Decision rules" R | ≥ 1.0 → GREEN | 0.92 (single-config) | YELLOW |
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| Phase 1 YELLOW rule M4 | mixed > pure-CPU baseline | 7.583 > 7.074 (+7.2 %) | **PASS** |
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| Phase 1 YELLOW rule for higgs | "concurrent-work win worth integration cost" | freed-core story (F4) makes a stronger case than 7 % alone | **PASS** |
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**Project continues to next kernel.** Phase 9 lessons → Phase 1 of
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the next kernel candidate (likely the VP9 / AV1 deblocking filter
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or CDEF — both have the same "small parallel block-level"
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characteristics and would amortise the M4 wins similarly).
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## Phase 7 M4 leaves open
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- **Power-draw delta (M7).** The Himbeere Fritz!DECT plug can give
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wall-power readings under each of the 5 configurations above.
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Critical for the higgs (battery) deployment argument; not
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measured this session. If mixed mode uses *less* wall power than
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NEON-4-alone while delivering 9 % more throughput, the
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energy-per-frame win compounds.
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- **Thermal sustained-load test.** All M4 runs were 8 seconds —
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far below any thermal-throttle window. A 5+ minute sustained
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mixed-load test on hertz with `vcgencmd measure_temp` polled
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would tell us whether the mixed mode is sustainable or just a
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burst peak.
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- **Realistic-workload coefficient distribution.** Phase 3 RNG
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generates roughly-uniformly-distributed coefficients; real VP9
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bitstreams are heavily skewed (DC-only fast path frequency ~10-30%
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in real content). The M2 / M3 / M4 numbers may shift under a
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realistic distribution; for Phase 1 closure this isn't load-bearing
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but Phase 8 should re-measure with a bitstream-derived sample.
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- **Multi-frame pipelining.** Current `vkQueueSubmit + vkQueueWaitIdle`
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is fully synchronous. Async double-buffering (submit frame N+1
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while frame N is in flight) could push QPU contribution up; this
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is the obvious next-kernel optimisation if the project continues.
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## Final phase-7 verdict
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```
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Phase 7 (v1) → loopback to Phase 4' (R=0.230, predicted=2.0)
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Phase 4' (v2-v5) → R = 0.92 (v4 production)
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Phase 7 M4 gate → mixed 7.583 > pure-CPU 7.074 ✓ PASS
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→ next-kernel cycle authorised
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```
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Per dev_process.md:
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> Phase 7 (Verification Measurements). Repeat measurements from
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> Phase 3. Compare explicitly against baseline. **If the delta
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> matches Phase 4's prediction → done.** [...] If not → loopback.
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Phase 4' predicted M4 outcome implicitly by predicting R ≥ 0.5
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would unlock the YELLOW concurrent-work scenario. That prediction
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landed (R = 0.92 single-config, mixed = +7 % over pure-CPU). Phase
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7 is **closed**. Next cycle of the loop opens at Phase 1 with the
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second kernel choice (recommend CDEF or deblocking per `phase0.md
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§5` codec-back-end-fits-QPU table).
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