marfrit
356e446a49
Third daedalus-fourier kernel — VP9 8-tap regular subpel filter,
horizontal direction, 8-wide output. Multiply-heavy by design to
stress V3D's no-DP4A deficit. Full cycle Phase 1-7 + M4'''.
Phase 5''' second-model review delivered cleanly — caught 1 RED
bug pre-implementation (src_off off-by-3 indexing convention) and
2 YELLOW gaps (assert MUST language, shaderdb filter-LUT gate).
Without the review, M1''' would have failed silently on first run
with cryptic "high-index source pixels wrong" symptoms.
Phase 6 v1 first-light: M1''' 100.0000% bit-exact (65536/65536
blocks across all 16 mx phases). Phase 5''' filter-LUT prediction
materialised exactly: 197 uniforms (gate was 144), 2 threads (down
from cycle-2's 4 due to register pressure).
Performance:
M2''' = 1.413 Mblock/s (707.9 ns/block)
M3''' = 20.997 Mblock/s (NEON baseline phase3)
R''' = 0.067 (RED band — structural mismatch)
shaderdb: 488 inst, 2 threads, 197 uniforms, 25 max-temps, 0 spills
M4''' concurrent matrix (8s windows):
NEON 1-core 14.479 Mblock/s
NEON 4-core 15.248 Mblock/s <- baseline (compute-bound,
not bandwidth-saturated
like cycles 1+2!)
QPU only 1.380 Mblock/s
MIXED NEON-3 + QPU 12.277 Mblock/s <- -19.5% (FAIL gate)
MIXED NEON-4 + QPU 12.158 Mblock/s <- -20.3%
NEW cross-cycle finding (Phase 9 lesson 2): compute-bound CPU
workloads make the QPU-offload story collapse. Cycles 1+2 were
bandwidth-saturated (4-core scaling 0.56-0.82x of 1-core), so
freeing a CPU core via QPU offload added throughput. Cycle 3 MC
is compute-bound (4-core scaling 1.05x of 1-core — near-linear),
no free cycles to free. QPU contribution (0.45 Mblock/s in
contention) doesn't compensate for losing 1 NEON core delivering
~3.8 Mblock/s.
But 30fps@1080p floor: PASS in every config (1.4x to 15.7x
isolation margin). Per project_30fps_floor_is_fine.md, user-facing
test never fails — daily YouTube playback works fine on any CPU/QPU
split.
DEPLOYMENT RECIPE for higgs (cycle 3 confirmed split):
IDCT (k1) -> QPU (R=0.92, +7% mixed, frees CPU core)
LPF (k2) -> QPU (R=0.41, +7% mixed, frees CPU core)
MC (k3) -> CPU (R=0.067, -19.5% mixed — stays on CPU)
Entropy -> CPU (structurally serial)
Mixed-substrate deployment, not "QPU does everything". Realistic for
higgs: entropy + MC on 2-3 ARM cores; IDCT + LPF dispatched to QPU
concurrently; 1-2 ARM cores left for vscode etc.
New artifacts:
- src/v3d_mc_8h.comp — GLSL kernel
- tests/vp9_mc_ref.c — standalone C ref (REGULAR filter
embedded; clean transcription)
- tests/bench_neon_mc.c — M1'''_c + M3''' bench
- tests/bench_v3d_mc.c — M1''' + M2''' bench with contract
asserts + 30fps margin display
- tests/bench_concurrent_mc.c — M4''' pthread bench
- external/ffmpeg-snapshot/libavcodec/aarch64/vp9mc_neon.S (vendored)
- external/ffmpeg-snapshot/libavcodec/vp9_subpel_filters_table.c
(hand-extracted; provides
ff_vp9_subpel_filters symbol
without dragging in full vp9dsp.c)
- docs/k3_mc_phase{1,2,3,4,5,7}.md — full cycle documentation
Memory updates: project_30fps_floor_is_fine.md (user's 30fps target
recalibration), MEMORY.md index updated.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
105 lines
3.9 KiB
Markdown
105 lines
3.9 KiB
Markdown
---
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cycle: 3
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phase: 1
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status: open
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date_opened: 2026-05-18
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parent_cycle: k2_deblock_phase7.md (cycle 2 closed YELLOW-via-M4'' PASS)
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target_kernel: VP9 8-tap MC interpolation, regular filter, horizontal, 8×N block
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dev_host: hertz
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---
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# Cycle 3, Phase 1 — MC interpolation kernel goal
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Per `k2_deblock_phase7.md` verdict (project continues). MC interpolation
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chosen because: most-common per-frame work in real bitstreams (every
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inter block); multiply-heavy → stresses V3D SMUL24 / lack of DP4A
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directly; VP9+AV1 both use the same 8-tap structure.
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## Kernel under test
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**VP9 8-tap regular subpel filter, horizontal direction, 8×N block,
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"put" (non-averaging) mode.**
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libavcodec symbol: `ff_vp9_put_8tap_regular_8h_neon` (and equivalents
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for smooth/sharp filter types). C reference: `put_8tap_regular_8h_c`
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from `libavcodec/vp9dsp_template.c` (instantiated via the
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`filter_fn_1d(8, h, mx, regular, FILTER_8TAP_REGULAR, put)` macro
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expansion).
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I/O contract (per VP9 spec § 8.5.1 — subpel motion compensation):
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```c
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void put_8tap_regular_8h_c(uint8_t *dst, ptrdiff_t dst_stride,
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const uint8_t *src, ptrdiff_t src_stride,
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int h, int mx, int my);
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```
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- `dst` : destination block, written
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- `dst_stride` : destination row stride
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- `src` : source block, read (with -3..+4 column overhang for horizontal)
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- `src_stride` : source row stride
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- `h` : block height (typically 8 for 8×8)
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- `mx` : x-axis subpel phase ∈ [0, 15]
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- `my` : y-axis subpel phase (unused for horizontal-only filter)
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Per output pixel:
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```
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out[r][c] = clip(sum_{k=0..7} filter[k] * src[r][c+k-3] + 64) >> 7
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```
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Filter coefficients: `ff_vp9_subpel_filters[FILTER_8TAP_REGULAR][mx][0..7]`
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(int16, signed; 16 phases; sum to 128).
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## Measurable success criteria (cycle-3 numbering)
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| ID | Measurement | Gate |
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|---|---|---|
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| **M1'''** | Bit-exact match rate vs C reference, ≥10 000 random 8×8 blocks (all 16 mx phases sampled) | 100.0000 % |
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| **M2'''** | QPU throughput in Mblock/s | recorded |
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| **M3'''** | NEON `ff_vp9_put_8tap_regular_8h_neon` throughput, single-core | recorded |
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| **M4'''** | MIXED NEON-3 + QPU vs pure NEON-4 (only if YELLOW band) | conditional |
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Derived: **R''' = M2''' / M3'''**.
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## Decision rules (same as cycle 1/2)
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R''' bands and verdicts unchanged (see `phase1.md` and `k2_deblock_phase1.md`).
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Cycle-2 calibration adjustment: ORANGE band (0.1 ≤ R''' < 0.5) is
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no longer auto-close — run M4''' regardless.
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Predicted R''' band: **0.4–0.8.**
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- MC is more compute-bound than LPF (8 mults + 7 adds per output
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pixel; 64 pixels per block → ~960 ops per block)
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- Bandwidth-equivalent to LPF (per-block ~120 B read + 64 B write
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≈ 184 B → similar 5-6 MB/frame at 32 400 blocks)
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- V3D SMUL24 covers the 8b×8b → 16b mults without overflow
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- But no DP4A means we lose the typical "4× INT8 speedup" CPUs get
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via SDOT — V3D does these as scalar SMUL24
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## Cycle 1+2 lessons baked in from start
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Per `k2_deblock_phase7.md §"Phase 9 lessons"`:
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1. WG=256, 2-per-subgroup adaptation, uint8_t SSBO, oob early-return,
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NO chained ternary — these are the v1 defaults.
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2. Phase 5 second-model review is mandatory.
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3. R isolation is misleading; M4''' is the real gate.
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4. Always-N-1-NEON + QPU recommended for higgs deployment (oversub
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hurts for lighter kernels).
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5. shaderdb at 4 threads / 0 spills = compiler delivered; further
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optimisation must target algorithm, not compile shape.
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## Phase 2 → Phase 3 hand-off
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Phase 2 must:
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- Vendor `libavcodec/aarch64/vp9mc_neon.S` from FFmpeg n7.1.3
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(matches existing snapshot pin)
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- Confirm `ff_vp9_subpel_filters` definition source
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(`libavcodec/vp9dsp.c:32`, just the 16 × 8 REGULAR row needed)
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- Pin the exact NEON symbol naming
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Phase 3 must:
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- Write standalone C ref (`tests/vp9_mc_ref.c`) with REGULAR filter
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table embedded
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- Write `tests/bench_neon_mc.c` (M1'''_c gate + M3''')
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- Capture M3''' before any QPU work
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