marfrit
356e446a49
Third daedalus-fourier kernel — VP9 8-tap regular subpel filter,
horizontal direction, 8-wide output. Multiply-heavy by design to
stress V3D's no-DP4A deficit. Full cycle Phase 1-7 + M4'''.
Phase 5''' second-model review delivered cleanly — caught 1 RED
bug pre-implementation (src_off off-by-3 indexing convention) and
2 YELLOW gaps (assert MUST language, shaderdb filter-LUT gate).
Without the review, M1''' would have failed silently on first run
with cryptic "high-index source pixels wrong" symptoms.
Phase 6 v1 first-light: M1''' 100.0000% bit-exact (65536/65536
blocks across all 16 mx phases). Phase 5''' filter-LUT prediction
materialised exactly: 197 uniforms (gate was 144), 2 threads (down
from cycle-2's 4 due to register pressure).
Performance:
M2''' = 1.413 Mblock/s (707.9 ns/block)
M3''' = 20.997 Mblock/s (NEON baseline phase3)
R''' = 0.067 (RED band — structural mismatch)
shaderdb: 488 inst, 2 threads, 197 uniforms, 25 max-temps, 0 spills
M4''' concurrent matrix (8s windows):
NEON 1-core 14.479 Mblock/s
NEON 4-core 15.248 Mblock/s <- baseline (compute-bound,
not bandwidth-saturated
like cycles 1+2!)
QPU only 1.380 Mblock/s
MIXED NEON-3 + QPU 12.277 Mblock/s <- -19.5% (FAIL gate)
MIXED NEON-4 + QPU 12.158 Mblock/s <- -20.3%
NEW cross-cycle finding (Phase 9 lesson 2): compute-bound CPU
workloads make the QPU-offload story collapse. Cycles 1+2 were
bandwidth-saturated (4-core scaling 0.56-0.82x of 1-core), so
freeing a CPU core via QPU offload added throughput. Cycle 3 MC
is compute-bound (4-core scaling 1.05x of 1-core — near-linear),
no free cycles to free. QPU contribution (0.45 Mblock/s in
contention) doesn't compensate for losing 1 NEON core delivering
~3.8 Mblock/s.
But 30fps@1080p floor: PASS in every config (1.4x to 15.7x
isolation margin). Per project_30fps_floor_is_fine.md, user-facing
test never fails — daily YouTube playback works fine on any CPU/QPU
split.
DEPLOYMENT RECIPE for higgs (cycle 3 confirmed split):
IDCT (k1) -> QPU (R=0.92, +7% mixed, frees CPU core)
LPF (k2) -> QPU (R=0.41, +7% mixed, frees CPU core)
MC (k3) -> CPU (R=0.067, -19.5% mixed — stays on CPU)
Entropy -> CPU (structurally serial)
Mixed-substrate deployment, not "QPU does everything". Realistic for
higgs: entropy + MC on 2-3 ARM cores; IDCT + LPF dispatched to QPU
concurrently; 1-2 ARM cores left for vscode etc.
New artifacts:
- src/v3d_mc_8h.comp — GLSL kernel
- tests/vp9_mc_ref.c — standalone C ref (REGULAR filter
embedded; clean transcription)
- tests/bench_neon_mc.c — M1'''_c + M3''' bench
- tests/bench_v3d_mc.c — M1''' + M2''' bench with contract
asserts + 30fps margin display
- tests/bench_concurrent_mc.c — M4''' pthread bench
- external/ffmpeg-snapshot/libavcodec/aarch64/vp9mc_neon.S (vendored)
- external/ffmpeg-snapshot/libavcodec/vp9_subpel_filters_table.c
(hand-extracted; provides
ff_vp9_subpel_filters symbol
without dragging in full vp9dsp.c)
- docs/k3_mc_phase{1,2,3,4,5,7}.md — full cycle documentation
Memory updates: project_30fps_floor_is_fine.md (user's 30fps target
recalibration), MEMORY.md index updated.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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72 lines
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---
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cycle: 3
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phase: 5
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status: closed 2026-05-18 — PASS-WITH-REVISIONS, revisions applied
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date_opened: 2026-05-18
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date_closed: 2026-05-18
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parent: k3_mc_phase4.md
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reviewer: Claude Sonnet (general-purpose Agent, fresh context)
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plan_author: Claude Opus 4.7 (this session)
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verdict: PASS-WITH-REVISIONS
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---
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# Cycle 3, Phase 5 — Second-Model Review of MC Plan
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Same handoff: in-session Agent (Sonnet, fresh context), files read
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direct from disk, 5 review prompts + "anything else."
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Outcome: **1 RED (off-by-3 `src_off` indexing bug)**, **2 YELLOW**
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(shaderdb LUT gate for filter table, "MUST" assert language for
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contracts). Cycle-1+2 RED patterns (write race, barrier UB,
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subgroup-ops table error) did not recur.
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**Phase 5 paid off again.** The RED would have caused a bit-exact
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mismatch on the first run with cryptic "high index source pixels are
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wrong" symptoms — likely 1-2 debug cycles to track down without the
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review.
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## Review (verbatim)
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````markdown
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## Verdict
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PASS-WITH-REVISIONS — no RED-class correctness bugs. Two YELLOW findings
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require plan amendments before Phase 6 proceeds. ...
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[full review preserved — reviewer's RED finding 4 traces the off-by-3:
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shader's `src_off = block_base + 3` + `src_stride_u8 = 16` + reading
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`s[0..14]` causes high-index reads to spill into next row]
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````
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*(Verbatim review in agent output; key findings paraphrased below.)*
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| # | Severity | Issue | Resolution |
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|---|---|---|---|
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| 1 (orientation) | GREEN | All 8 oN expressions stencil-aligned correctly | accepted |
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| 2 (filter LUT) | YELLOW | `const int FILTER_REGULAR[16][8]` may inflate uniform count or compile to large LUT | Phase 6 to record uniform count via `V3D_DEBUG=shaderdb`; if >~144 uniforms, escalate filter to SSBO binding 3 |
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| 3 (race safety) | GREEN-w/note | `stride ≥ 8` contract correct; phrasing softer than cycle-2 standard | applied: §5 MUST assert |
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| 4 (`src_off` semantics) | **RED** | Plan said "src_off mirrors src+3"; with stride=16 shader's `s13`/`s14` read into next row's first 2 bytes | **applied: src_off = raw block base (no +3 shift); shader reads s[0..14] from there** |
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| 5 (missing) | GREEN-w/note | Coefficient overflow safely fits int32 (worked bound); no missing barrier-UB or write-race issues | accepted |
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| 6 (assert MUST language) | YELLOW | "Bench enforces with asserts" softer than cycle-2 MUST pattern | applied: §5 MUST language |
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| 7 (no barrier OK) | GREEN | Cycle-1 finding-7 doesn't apply (no barrier) | accepted |
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| 8 (filter table matches) | GREEN | `vp9_mc_ref.c` filter values match `vp9_subpel_filters_table.c[1]` verbatim | accepted |
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## Resolution (applied to phase4 inline)
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1. **§4** — Clarified `src_off` is the byte offset of the **first byte
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of the source block in the SSBO buffer** (NOT shifted by +3). The
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C bench's `src + 3` C-caller convention does NOT carry into the
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SSBO offset. Shader reads `s[k] = u_src.src[src_off + row*stride + k]`
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for k=0..14, which equals `master_src[block_base + row*stride + k]`,
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matching the C ref's per-row read of `master_src[block_base + row*stride + (x..x+7)]`
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for output col x ∈ 0..7.
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2. **§5** — Hardened "Bench enforces" to "Phase 6 MUST add
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`assert(dst_stride_u8 >= 8 && src_stride_u8 >= 15)` in
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`bench_v3d_mc.c`'s meta-construction loop." Cycle-2 finding-4
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pattern applied.
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3. **§5** — Added: "Phase 6 MUST run `V3D_DEBUG=shaderdb` after first
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compile and record uniform count. If uniform count > ~144,
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escalate filter to a dedicated SSBO binding 3."
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After revisions: **Phase 4''' APPROVED for Phase 6''' implementation.**
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