marfrit
f92dc40f43
H.264 scope added 2026-05-18 per user direction. Pi 5's VideoCore VII has no hardware H.264 decoder block (only HEVC), so a QPU-accelerated H.264 path fills the most impactful codec gap. Cycle 6 = first H.264 kernel (4x4 IDCT + add, smallest H.264 transform, simplest first cycle). Phase 1: goal doc + 1080p30 floor analysis (5.85 Mblock/s worst-case, 2.0 Mblock/s realistic since most MBs use 8x8 or P-skip). Phase 3: NEON M3 baseline captured. ff_h264_idct_add_neon on hertz delivers 175 Mblock/s (5.7 ns per block) = 30x worst-case floor margin. H.264 IDCT 4x4 is dramatically lighter than VP9 IDCT 8x8 (21x faster per block). Phase 3 closure also caught the key Phase 9 lesson: H.264/FFmpeg blocks are COLUMN-MAJOR (block[c*4 + r] = (row=r, col=c)). NEON ld1 with 4 registers interleaves loading, and the FFmpeg C ref indexing makes this convention explicit. Initial C ref assumed row-major, M1 was 5% bit-exact; after fix, M1 = 100%. Convention encoded for all subsequent H.264 cycles (cycle 7+). - external/ffmpeg-snapshot/libavcodec/aarch64/h264idct_neon.S (vendored verbatim from FFmpeg n7.1.3, 415 lines) - external/ffmpeg-snapshot/PROVENANCE.md: updated - tests/h264_idct4_ref.c: column-major C ref - tests/bench_neon_h264idct4.c: M1 + M3 bench - CMakeLists.txt: cycle 6 NEON bench wiring - docs/k6_h264idct4_phase1.md, phase3.md Phase 4 next: QPU shader for cycle 6. Predicted R6 = 0.01 (deep RED — kernel too small relative to QPU dispatch overhead) but worth building for cycle-completeness + the opportunistic-helper hypothesis (cycle 6 may stay CPU per recipe). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
120 lines
4.1 KiB
Markdown
120 lines
4.1 KiB
Markdown
---
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cycle: 6
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phase: 1
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status: open
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date_opened: 2026-05-18
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codec: H.264
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kernel: IDCT 4x4 + add (intra-block residual)
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parent: project_h264_scope_added.md (memory)
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---
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# Cycle 6, Phase 1 — H.264 IDCT 4×4 + add
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First H.264 kernel. Per `project_h264_scope_added`, the user
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added H.264 to daedalus-fourier scope 2026-05-18 because Pi 5
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has no hardware H.264 decoder despite H.264 being the most
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common web codec.
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## Why IDCT 4×4 first
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- **Smallest H.264 transform.** 16 coefficients per block, 4×4
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output pixels. Simpler than VP9 IDCT 8×8 (cycle 1, 64 coefs).
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- **Most-used.** H.264 macroblocks default to 4×4 intra
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prediction + residual; 8×8 is High-profile only. 4×4 hits
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most real-world H.264 streams.
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- **Predicted GREEN.** Per the cycle 1-5 bandwidth-bound vs
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compute-bound classification: 4×4 IDCT is bandwidth-bound
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(16 reads, 16 writes, ~20 ALU ops/output). Should map well
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to V3D 7.1 compute.
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- **Clean reference.** FFmpeg's `ff_h264_idct_add_neon` is
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standalone (no eob parameter, no complex DC dispatch). Single
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call computes 1 block of IDCT + add.
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## Kernel contract
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Per H.264 spec §8.5.12, the inverse transform is an
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integer-arithmetic transform (no rounding-by-cosine like VP9's
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Q14 trig math). Each 4×4 block:
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1. Inverse row transform (4 row passes, each one 1D IDCT-like
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integer butterfly).
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2. Inverse column transform (4 column passes, same butterfly).
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3. Round and add to `dst[r,c] = clamp(dst[r,c] + ((idct[r,c] + 32) >> 6), 0, 255)`.
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Spec coefficients (Hadamard-like with 1/2 scaling):
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```
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[1 1 1 1/2]
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[1 1/2 -1 -1]
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[1 -1/2 -1 1]
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[1 -1 1 -1/2]
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```
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Integer form scales by 2: replace 1/2 with 1 and ½ with right-
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shift in the round step.
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## NEON reference (M3 target)
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FFmpeg's `ff_h264_idct_add_neon`
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(external/ffmpeg-snapshot/libavcodec/aarch64/h264idct_neon.S
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line 25, 56 instructions of NEON asm). Signature:
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```
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void ff_h264_idct_add_neon(uint8_t *dst, int16_t *block, ptrdiff_t stride);
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```
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- `dst`: 4×4 pixel block in 8-bit luma surface, `stride` between rows.
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- `block`: 16 int16 coefficients (row-major).
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- destructively clears `block` to zero after the transform (per H.264 conformance).
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## 30fps@1080p H.264 floor
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H.264 1080p uses 16×16 macroblocks with up to 16 4×4 blocks per MB.
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Luma: (1920/16) × (1080/16) = 120 × 67.5 = 8100 MB/frame ×
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16 blocks/MB = 129 600 4×4 blocks/frame. Plus chroma: 4 + 4 = 8
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chroma 4×4 per MB × 8100 = 64 800 chroma blocks. Total: ~195k
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4×4 blocks/frame max (worst case; many real MBs use 8×8 or skip).
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At 30fps: ~5.85 Mblock/s required for full-frame 4×4 worst case.
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A more realistic average (many MBs use 8×8, P-skip, etc.) is
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~2 Mblock/s.
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**30fps@1080p H.264 4×4 floor (realistic): 2 Mblock/s.**
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**30fps@1080p H.264 4×4 floor (worst case): 5.85 Mblock/s.**
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## R-band decision rules (carried from phase1.md)
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- R ≥ 1.0 → **GREEN** (QPU faster than NEON-1 in isolation).
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- 0.5 ≤ R < 1.0 → **YELLOW** (M4 decides).
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- 0.1 ≤ R < 0.5 → **ORANGE** (M4 may rescue).
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- R < 0.1 → **RED** (structural mismatch).
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Floor margin: ratio of M2 (or M3 if CPU-only) over the 5.85
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Mblock/s worst-case 30fps floor.
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## Acceptance for Phase 7
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- M1: 100.0000% bit-exact (QPU output vs C ref, 10000+ random
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blocks). Same standard as cycles 1-5.
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- M2: captured, classified per R band.
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- M4: same-kernel mixed-bench measured (with Issue 003 caveats —
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this is the worst-case framing).
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- 30fps@1080p H.264 4×4 floor margin reported.
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## Cycle 6 deliverables
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1. `external/ffmpeg-snapshot/libavcodec/aarch64/h264idct_neon.S`
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(vendored 2026-05-18, this phase).
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2. `tests/h264_idct4_ref.c` — standalone C reference (LGPL-2.1+
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transcribed from spec).
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3. `tests/bench_neon_h264idct4.c` — Phase 3 M3 bench.
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4. `src/v3d_h264idct4.comp` — Phase 6 QPU shader.
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5. `tests/bench_v3d_h264idct4.c` — Phase 6+7 M1+M2 bench (3-way
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vs NEON + C ref).
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6. M4: extend `bench_concurrent_mixed.c` with K_H264_IDCT4.
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7. Phase 4-7 docs.
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## Next step (within this phase)
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Move to Phase 3 (NEON baseline M3) after writing the C
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reference. Phase 2 (libavcodec inventory) is implicit since we
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know the kernel from the FFmpeg vendor.
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