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Rosenblatt Phase-2: userspace regcmd builder — U3 wrapper + CNA stage (4a)

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- librocket.{c,h}: thin ioctl wrapper over the rocket accel uAPI (open + CREATE_BO/
  SUBMIT/PREP_BO/FINI_BO + mmap). Compiles with -I/usr/include/drm.
- rkt_matmul_cna.{c,h} + cna_defs.h: CNA-stage regcmd emit for an INT8 matmul-as-
  1x1-conv, faithful port of Mesa rocket fill_first_regcmd's CNA section. Compiles
  clean (-Wall -Wextra), 85 emits. Cross-validated: two independent ports (dspark
  Montessori-scaffolded + big-pickle autonomous) agree at the emit level.
- rkt_matmul_coredpu.{c,h} + coredpu_defs.h: CORE+DPU+PC scaffold (empty body,
  @@INSERT@@ marker). Params struct incl. float scales + 3 DMA-addr fields.
  Body port is WIP: 82 DPU emits + float requant + PC tail remain (needs slicing).
- *_reference.txt: curated Mesa rocket emit excerpts + register defines (implementer
  reference bundles).

Implementer: dspark (DeepSeek-V4-Flash NVFP4, local) via Montessori scaffolding;
autonomous CNA also produced by opencode/big-pickle. Multi-model benchmark in
claude-memory reference_dspark_implementer. NOT golden-verified (faithful-to-Mesa;
needs a Mesa build or NPU hardware to byte-check).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01EWpfhDgYNA21tETDP9ueBE
This commit is contained in:
claude-noether
2026-07-13 19:23:34 +00:00
parent c9a3f5c600
commit 60e7709d7b
13 changed files with 3796 additions and 0 deletions
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userspace/npu-probe/.gitignore
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*.o
userspace/npu-probe/cna_defs.h
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#ifndef CNA_DEFS_H
#define CNA_DEFS_H
#define REG_CNA_S_STATUS 0x00001000
#define CNA_S_STATUS_RESERVED_0__MASK 0xfffc0000
#define CNA_S_STATUS_RESERVED_0__SHIFT 18
#define CNA_S_STATUS_STATUS_1__MASK 0x00030000
#define CNA_S_STATUS_STATUS_1__SHIFT 16
#define CNA_S_STATUS_RESERVED_1__MASK 0x0000fffc
#define CNA_S_STATUS_RESERVED_1__SHIFT 2
#define CNA_S_STATUS_STATUS_0__MASK 0x00000003
#define CNA_S_STATUS_STATUS_0__SHIFT 0
#define REG_CNA_S_POINTER 0x00001004
#define CNA_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define CNA_S_POINTER_RESERVED_0__SHIFT 17
#define CNA_S_POINTER_EXECUTER__MASK 0x00010000
#define CNA_S_POINTER_EXECUTER__SHIFT 16
#define CNA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define CNA_S_POINTER_RESERVED_1__SHIFT 6
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define CNA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define CNA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define CNA_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define CNA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define CNA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define CNA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define CNA_S_POINTER_POINTER_PP_EN__SHIFT 1
#define CNA_S_POINTER_POINTER__MASK 0x00000001
#define CNA_S_POINTER_POINTER__SHIFT 0
#define REG_CNA_OPERATION_ENABLE 0x00001008
#define CNA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define CNA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define CNA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define CNA_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_CNA_CONV_CON1 0x0000100c
#define CNA_CONV_CON1_RESERVED_0__MASK 0x80000000
#define CNA_CONV_CON1_RESERVED_0__SHIFT 31
#define CNA_CONV_CON1_NONALIGN_DMA__MASK 0x40000000
#define CNA_CONV_CON1_NONALIGN_DMA__SHIFT 30
#define CNA_CONV_CON1_GROUP_LINE_OFF__MASK 0x20000000
#define CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT 29
#define CNA_CONV_CON1_RESERVED_1__MASK 0x1ffe0000
#define CNA_CONV_CON1_RESERVED_1__SHIFT 17
#define CNA_CONV_CON1_DECONV__MASK 0x00010000
#define CNA_CONV_CON1_DECONV__SHIFT 16
#define CNA_CONV_CON1_ARGB_IN__MASK 0x0000f000
#define CNA_CONV_CON1_ARGB_IN__SHIFT 12
#define CNA_CONV_CON1_RESERVED_2__MASK 0x00000c00
#define CNA_CONV_CON1_RESERVED_2__SHIFT 10
#define CNA_CONV_CON1_PROC_PRECISION__MASK 0x00000380
#define CNA_CONV_CON1_PROC_PRECISION__SHIFT 7
#define CNA_CONV_CON1_IN_PRECISION__MASK 0x00000070
#define CNA_CONV_CON1_IN_PRECISION__SHIFT 4
#define CNA_CONV_CON1_CONV_MODE__MASK 0x0000000f
#define CNA_CONV_CON1_CONV_MODE__SHIFT 0
#define REG_CNA_CONV_CON2 0x00001010
#define CNA_CONV_CON2_RESERVED_0__MASK 0xff000000
#define CNA_CONV_CON2_RESERVED_0__SHIFT 24
#define CNA_CONV_CON2_KERNEL_GROUP__MASK 0x00ff0000
#define CNA_CONV_CON2_KERNEL_GROUP__SHIFT 16
#define CNA_CONV_CON2_RESERVED_1__MASK 0x0000c000
#define CNA_CONV_CON2_RESERVED_1__SHIFT 14
#define CNA_CONV_CON2_FEATURE_GRAINS__MASK 0x00003ff0
#define CNA_CONV_CON2_FEATURE_GRAINS__SHIFT 4
#define CNA_CONV_CON2_RESERVED_2__MASK 0x00000008
#define CNA_CONV_CON2_RESERVED_2__SHIFT 3
#define CNA_CONV_CON2_CSC_WO_EN__MASK 0x00000004
#define CNA_CONV_CON2_CSC_WO_EN__SHIFT 2
#define CNA_CONV_CON2_CSC_DO_EN__MASK 0x00000002
#define CNA_CONV_CON2_CSC_DO_EN__SHIFT 1
#define CNA_CONV_CON2_CMD_FIFO_SRST__MASK 0x00000001
#define CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT 0
#define REG_CNA_CONV_CON3 0x00001014
#define CNA_CONV_CON3_RESERVED_0__MASK 0x80000000
#define CNA_CONV_CON3_RESERVED_0__SHIFT 31
#define CNA_CONV_CON3_NN_MODE__MASK 0x70000000
#define CNA_CONV_CON3_NN_MODE__SHIFT 28
#define CNA_CONV_CON3_RESERVED_1__MASK 0x0c000000
#define CNA_CONV_CON3_RESERVED_1__SHIFT 26
#define CNA_CONV_CON3_ATROUS_Y_DILATION__MASK 0x03e00000
#define CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT 21
#define CNA_CONV_CON3_ATROUS_X_DILATION__MASK 0x001f0000
#define CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT 16
#define CNA_CONV_CON3_RESERVED_2__MASK 0x0000c000
#define CNA_CONV_CON3_RESERVED_2__SHIFT 14
#define CNA_CONV_CON3_DECONV_Y_STRIDE__MASK 0x00003800
#define CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT 11
#define CNA_CONV_CON3_DECONV_X_STRIDE__MASK 0x00000700
#define CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT 8
#define CNA_CONV_CON3_RESERVED_3__MASK 0x000000c0
#define CNA_CONV_CON3_RESERVED_3__SHIFT 6
#define CNA_CONV_CON3_CONV_Y_STRIDE__MASK 0x00000038
#define CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT 3
#define CNA_CONV_CON3_CONV_X_STRIDE__MASK 0x00000007
#define CNA_CONV_CON3_CONV_X_STRIDE__SHIFT 0
#define REG_CNA_DATA_SIZE0 0x00001020
#define CNA_DATA_SIZE0_RESERVED_0__MASK 0xf8000000
#define CNA_DATA_SIZE0_RESERVED_0__SHIFT 27
#define CNA_DATA_SIZE0_DATAIN_WIDTH__MASK 0x07ff0000
#define CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT 16
#define CNA_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
#define CNA_DATA_SIZE0_RESERVED_1__SHIFT 11
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK 0x000007ff
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT 0
#define REG_CNA_DATA_SIZE1 0x00001024
#define CNA_DATA_SIZE1_RESERVED_0__MASK 0xc0000000
#define CNA_DATA_SIZE1_RESERVED_0__SHIFT 30
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK 0x3fff0000
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT 16
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK 0x0000ffff
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT 0
#define REG_CNA_DATA_SIZE2 0x00001028
#define CNA_DATA_SIZE2_RESERVED_0__MASK 0xfffff800
#define CNA_DATA_SIZE2_RESERVED_0__SHIFT 11
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK 0x000007ff
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT 0
#define REG_CNA_DATA_SIZE3 0x0000102c
#define CNA_DATA_SIZE3_RESERVED_0__MASK 0xff000000
#define CNA_DATA_SIZE3_RESERVED_0__SHIFT 24
#define CNA_DATA_SIZE3_SURF_MODE__MASK 0x00c00000
#define CNA_DATA_SIZE3_SURF_MODE__SHIFT 22
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK 0x003fffff
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT 0
#define REG_CNA_WEIGHT_SIZE0 0x00001030
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK 0xffffffff
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT 0
#define REG_CNA_WEIGHT_SIZE1 0x00001034
#define CNA_WEIGHT_SIZE1_RESERVED_0__MASK 0xfff80000
#define CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT 19
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK 0x0007ffff
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT 0
#define REG_CNA_WEIGHT_SIZE2 0x00001038
#define CNA_WEIGHT_SIZE2_RESERVED_0__MASK 0xe0000000
#define CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT 29
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK 0x1f000000
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT 24
#define CNA_WEIGHT_SIZE2_RESERVED_1__MASK 0x00e00000
#define CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT 21
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK 0x001f0000
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT 16
#define CNA_WEIGHT_SIZE2_RESERVED_2__MASK 0x0000c000
#define CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT 14
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK 0x00003fff
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT 0
#define REG_CNA_CBUF_CON0 0x00001040
#define CNA_CBUF_CON0_RESERVED_0__MASK 0xffffc000
#define CNA_CBUF_CON0_RESERVED_0__SHIFT 14
#define CNA_CBUF_CON0_WEIGHT_REUSE__MASK 0x00002000
#define CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT 13
#define CNA_CBUF_CON0_DATA_REUSE__MASK 0x00001000
#define CNA_CBUF_CON0_DATA_REUSE__SHIFT 12
#define CNA_CBUF_CON0_RESERVED_1__MASK 0x00000800
#define CNA_CBUF_CON0_RESERVED_1__SHIFT 11
#define CNA_CBUF_CON0_FC_DATA_BANK__MASK 0x00000700
#define CNA_CBUF_CON0_FC_DATA_BANK__SHIFT 8
#define CNA_CBUF_CON0_WEIGHT_BANK__MASK 0x000000f0
#define CNA_CBUF_CON0_WEIGHT_BANK__SHIFT 4
#define CNA_CBUF_CON0_DATA_BANK__MASK 0x0000000f
#define CNA_CBUF_CON0_DATA_BANK__SHIFT 0
#define REG_CNA_CBUF_CON1 0x00001044
#define CNA_CBUF_CON1_RESERVED_0__MASK 0xffffc000
#define CNA_CBUF_CON1_RESERVED_0__SHIFT 14
#define CNA_CBUF_CON1_DATA_ENTRIES__MASK 0x00003fff
#define CNA_CBUF_CON1_DATA_ENTRIES__SHIFT 0
#define REG_CNA_CVT_CON0 0x0000104c
#define CNA_CVT_CON0_RESERVED_0__MASK 0xf0000000
#define CNA_CVT_CON0_RESERVED_0__SHIFT 28
#define CNA_CVT_CON0_CVT_TRUNCATE_3__MASK 0x0fc00000
#define CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT 22
#define CNA_CVT_CON0_CVT_TRUNCATE_2__MASK 0x003f0000
#define CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT 16
#define CNA_CVT_CON0_CVT_TRUNCATE_1__MASK 0x0000fc00
#define CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT 10
#define CNA_CVT_CON0_CVT_TRUNCATE_0__MASK 0x000003f0
#define CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT 4
#define CNA_CVT_CON0_DATA_SIGN__MASK 0x00000008
#define CNA_CVT_CON0_DATA_SIGN__SHIFT 3
#define CNA_CVT_CON0_ROUND_TYPE__MASK 0x00000004
#define CNA_CVT_CON0_ROUND_TYPE__SHIFT 2
#define CNA_CVT_CON0_CVT_TYPE__MASK 0x00000002
#define CNA_CVT_CON0_CVT_TYPE__SHIFT 1
#define CNA_CVT_CON0_CVT_BYPASS__MASK 0x00000001
#define CNA_CVT_CON0_CVT_BYPASS__SHIFT 0
#define REG_CNA_CVT_CON1 0x00001050
#define CNA_CVT_CON1_CVT_SCALE0__MASK 0xffff0000
#define CNA_CVT_CON1_CVT_SCALE0__SHIFT 16
#define CNA_CVT_CON1_CVT_OFFSET0__MASK 0x0000ffff
#define CNA_CVT_CON1_CVT_OFFSET0__SHIFT 0
#define REG_CNA_CVT_CON2 0x00001054
#define CNA_CVT_CON2_CVT_SCALE1__MASK 0xffff0000
#define CNA_CVT_CON2_CVT_SCALE1__SHIFT 16
#define CNA_CVT_CON2_CVT_OFFSET1__MASK 0x0000ffff
#define CNA_CVT_CON2_CVT_OFFSET1__SHIFT 0
#define REG_CNA_CVT_CON3 0x00001058
#define CNA_CVT_CON3_CVT_SCALE2__MASK 0xffff0000
#define CNA_CVT_CON3_CVT_SCALE2__SHIFT 16
#define CNA_CVT_CON3_CVT_OFFSET2__MASK 0x0000ffff
#define CNA_CVT_CON3_CVT_OFFSET2__SHIFT 0
#define REG_CNA_CVT_CON4 0x0000105c
#define CNA_CVT_CON4_CVT_SCALE3__MASK 0xffff0000
#define CNA_CVT_CON4_CVT_SCALE3__SHIFT 16
#define CNA_CVT_CON4_CVT_OFFSET3__MASK 0x0000ffff
#define CNA_CVT_CON4_CVT_OFFSET3__SHIFT 0
#define REG_CNA_FC_CON0 0x00001060
#define CNA_FC_CON0_FC_SKIP_DATA__MASK 0xffff0000
#define CNA_FC_CON0_FC_SKIP_DATA__SHIFT 16
#define CNA_FC_CON0_RESERVED_0__MASK 0x0000fffe
#define CNA_FC_CON0_RESERVED_0__SHIFT 1
#define CNA_FC_CON0_FC_SKIP_EN__MASK 0x00000001
#define CNA_FC_CON0_FC_SKIP_EN__SHIFT 0
#define REG_CNA_FC_CON1 0x00001064
#define CNA_FC_CON1_RESERVED_0__MASK 0xfffe0000
#define CNA_FC_CON1_RESERVED_0__SHIFT 17
#define CNA_FC_CON1_DATA_OFFSET__MASK 0x0001ffff
#define CNA_FC_CON1_DATA_OFFSET__SHIFT 0
#define REG_CNA_PAD_CON0 0x00001068
#define CNA_PAD_CON0_RESERVED_0__MASK 0xffffff00
#define CNA_PAD_CON0_RESERVED_0__SHIFT 8
#define CNA_PAD_CON0_PAD_LEFT__MASK 0x000000f0
#define CNA_PAD_CON0_PAD_LEFT__SHIFT 4
#define CNA_PAD_CON0_PAD_TOP__MASK 0x0000000f
#define CNA_PAD_CON0_PAD_TOP__SHIFT 0
#define REG_CNA_FEATURE_DATA_ADDR 0x00001070
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK 0xffffffff
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT 0
#define REG_CNA_FC_CON2 0x00001074
#define CNA_FC_CON2_RESERVED_0__MASK 0xfffe0000
#define CNA_FC_CON2_RESERVED_0__SHIFT 17
#define CNA_FC_CON2_WEIGHT_OFFSET__MASK 0x0001ffff
#define CNA_FC_CON2_WEIGHT_OFFSET__SHIFT 0
#define REG_CNA_DMA_CON0 0x00001078
#define CNA_DMA_CON0_OV4K_BYPASS__MASK 0x80000000
#define CNA_DMA_CON0_OV4K_BYPASS__SHIFT 31
#define CNA_DMA_CON0_RESERVED_0__MASK 0x7ff00000
#define CNA_DMA_CON0_RESERVED_0__SHIFT 20
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK 0x000f0000
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT 16
#define CNA_DMA_CON0_RESERVED_1__MASK 0x0000fff0
#define CNA_DMA_CON0_RESERVED_1__SHIFT 4
#define CNA_DMA_CON0_DATA_BURST_LEN__MASK 0x0000000f
#define CNA_DMA_CON0_DATA_BURST_LEN__SHIFT 0
#define REG_CNA_DMA_CON1 0x0000107c
#define CNA_DMA_CON1_RESERVED_0__MASK 0xf0000000
#define CNA_DMA_CON1_RESERVED_0__SHIFT 28
#define CNA_DMA_CON1_LINE_STRIDE__MASK 0x0fffffff
#define CNA_DMA_CON1_LINE_STRIDE__SHIFT 0
#define REG_CNA_DMA_CON2 0x00001080
#define CNA_DMA_CON2_RESERVED_0__MASK 0xf0000000
#define CNA_DMA_CON2_RESERVED_0__SHIFT 28
#define CNA_DMA_CON2_SURF_STRIDE__MASK 0x0fffffff
#define CNA_DMA_CON2_SURF_STRIDE__SHIFT 0
#define REG_CNA_FC_DATA_SIZE0 0x00001084
#define CNA_FC_DATA_SIZE0_RESERVED_0__MASK 0xc0000000
#define CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT 30
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK 0x3fff0000
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT 16
#define CNA_FC_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
#define CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT 11
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK 0x000007ff
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT 0
#define REG_CNA_FC_DATA_SIZE1 0x00001088
#define CNA_FC_DATA_SIZE1_RESERVED_0__MASK 0xffff0000
#define CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT 16
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK 0x0000ffff
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT 0
#define REG_CNA_CLK_GATE 0x00001090
#define CNA_CLK_GATE_RESERVED_0__MASK 0xffffffe0
#define CNA_CLK_GATE_RESERVED_0__SHIFT 5
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK 0x00000010
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT 4
#define CNA_CLK_GATE_RESERVED_1__MASK 0x00000008
#define CNA_CLK_GATE_RESERVED_1__SHIFT 3
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK 0x00000004
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT 2
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK 0x00000002
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT 1
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK 0x00000001
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT 0
#define REG_CNA_DCOMP_CTRL 0x00001100
#define CNA_DCOMP_CTRL_RESERVED_0__MASK 0xfffffff0
#define CNA_DCOMP_CTRL_RESERVED_0__SHIFT 4
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK 0x00000008
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT 3
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK 0x00000007
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT 0
#define REG_CNA_DCOMP_REGNUM 0x00001104
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK 0xffffffff
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT 0
#define REG_CNA_DCOMP_ADDR0 0x00001110
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK 0xffffffff
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT0 0x00001140
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT1 0x00001144
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT2 0x00001148
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT3 0x0000114c
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT4 0x00001150
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT5 0x00001154
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT6 0x00001158
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT7 0x0000115c
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT8 0x00001160
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT9 0x00001164
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT10 0x00001168
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT11 0x0000116c
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT12 0x00001170
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT13 0x00001174
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT14 0x00001178
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT15 0x0000117c
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT 0
#define REG_CNA_CVT_CON5 0x00001180
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK 0xffffffff
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT 0
#define REG_CNA_PAD_CON1 0x00001184
#define CNA_PAD_CON1_PAD_VALUE__MASK 0xffffffff
#define CNA_PAD_CON1_PAD_VALUE__SHIFT 0
#define REG_DPU_S_POINTER 0x00004004
#define DPU_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define DPU_S_POINTER_RESERVED_0__SHIFT 17
#define DPU_S_POINTER_EXECUTER__MASK 0x00010000
#define DPU_S_POINTER_EXECUTER__SHIFT 16
#define DPU_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define DPU_S_POINTER_RESERVED_1__SHIFT 6
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define DPU_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define DPU_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define DPU_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define DPU_S_POINTER_POINTER_PP_EN__SHIFT 1
#define DPU_S_POINTER_POINTER__MASK 0x00000001
#define DPU_S_POINTER_POINTER__SHIFT 0
#define REG_DPU_RDMA_RDMA_S_STATUS 0x00005000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK 0xfffc0000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT 18
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK 0x00030000
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT 16
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK 0x0000fffc
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT 2
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK 0x00000003
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_S_POINTER 0x00005004
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT 17
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK 0x00010000
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT 16
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT 6
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT 1
#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK 0x00000001
#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT 0
#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE 0x00005008
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH 0x0000500c
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT 0x00005010
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xe0000000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 29
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK 0x1fff0000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT 16
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x0000e000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL 0x00005014
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR 0x00005018
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_BRDMA_CFG 0x0000501c
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK 0xffffffe0
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT 5
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK 0x0000001e
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT 1
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK 0x00000001
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT 0
#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR 0x00005020
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_NRDMA_CFG 0x00005028
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK 0xffffffe0
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT 5
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK 0x0000001e
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT 1
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK 0x00000001
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT 0
#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR 0x0000502c
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_ERDMA_CFG 0x00005034
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK 0xc0000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT 30
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK 0x20000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT 29
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK 0x10000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT 28
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK 0x0ffffff0
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT 4
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK 0x0000000c
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT 2
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK 0x00000002
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT 1
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK 0x00000001
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR 0x00005038
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE 0x00005040
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK 0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT 4
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG 0x00005044
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK 0xfffc0000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT 18
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK 0x00038000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT 15
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK 0x00007800
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT 11
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK 0x00000700
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT 8
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK 0x000000e0
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT 5
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK 0x00000010
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT 4
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK 0x00000008
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT 3
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000006
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT 1
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG 0x00005048
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK 0xfff80000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT 19
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK 0x0007c000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT 14
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK 0x00002000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT 13
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK 0x00001000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT 12
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK 0x00000e00
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT 9
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK 0x000001c0
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT 6
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK 0x00000038
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT 3
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK 0x00000007
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT 0
#define REG_DPU_RDMA_RDMA_SURF_NOTCH 0x0000504c
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK 0xfffffff0
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT 4
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_PAD_CFG 0x00005064
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK 0xffff0000
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT 16
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK 0x0000ff80
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT 7
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK 0x00000070
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT 4
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK 0x00000008
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT 3
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK 0x00000007
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT 0
#define REG_DPU_RDMA_RDMA_WEIGHT 0x00005068
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK 0xff000000
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT 24
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK 0x00ff0000
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT 16
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK 0x0000ff00
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT 8
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK 0x000000ff
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH 0x0000506c
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK 0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT 4
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT 0
#endif
userspace/npu-probe/cna_reference.txt
+704
View File
@@ -0,0 +1,704 @@
// ============ REGCMD PACKING ============
// Each register command is one uint64_t: (target<<48) | (value<<16) | reg
// where target = block_enum + 1. Block enums:
// PC=0x100 CNA=0x200 CORE=0x800 DPU=0x1000
// So CNA registers pack with target 0x201, DPU registers with target 0x1001.
// A field is set as: (value << FIELD__SHIFT) & FIELD__MASK and OR'd together.
// ============ REGISTER + FIELD DEFINES (from Mesa rkt_registers.h) ============
#define REG_CNA_S_STATUS 0x00001000
#define CNA_S_STATUS_RESERVED_0__MASK 0xfffc0000
#define CNA_S_STATUS_RESERVED_0__SHIFT 18
#define CNA_S_STATUS_STATUS_1__MASK 0x00030000
#define CNA_S_STATUS_STATUS_1__SHIFT 16
#define CNA_S_STATUS_RESERVED_1__MASK 0x0000fffc
#define CNA_S_STATUS_RESERVED_1__SHIFT 2
#define CNA_S_STATUS_STATUS_0__MASK 0x00000003
#define CNA_S_STATUS_STATUS_0__SHIFT 0
#define REG_CNA_S_POINTER 0x00001004
#define CNA_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define CNA_S_POINTER_RESERVED_0__SHIFT 17
#define CNA_S_POINTER_EXECUTER__MASK 0x00010000
#define CNA_S_POINTER_EXECUTER__SHIFT 16
#define CNA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define CNA_S_POINTER_RESERVED_1__SHIFT 6
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define CNA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define CNA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define CNA_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define CNA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define CNA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define CNA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define CNA_S_POINTER_POINTER_PP_EN__SHIFT 1
#define CNA_S_POINTER_POINTER__MASK 0x00000001
#define CNA_S_POINTER_POINTER__SHIFT 0
#define REG_CNA_OPERATION_ENABLE 0x00001008
#define CNA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define CNA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define CNA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define CNA_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_CNA_CONV_CON1 0x0000100c
#define CNA_CONV_CON1_RESERVED_0__MASK 0x80000000
#define CNA_CONV_CON1_RESERVED_0__SHIFT 31
#define CNA_CONV_CON1_NONALIGN_DMA__MASK 0x40000000
#define CNA_CONV_CON1_NONALIGN_DMA__SHIFT 30
#define CNA_CONV_CON1_GROUP_LINE_OFF__MASK 0x20000000
#define CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT 29
#define CNA_CONV_CON1_RESERVED_1__MASK 0x1ffe0000
#define CNA_CONV_CON1_RESERVED_1__SHIFT 17
#define CNA_CONV_CON1_DECONV__MASK 0x00010000
#define CNA_CONV_CON1_DECONV__SHIFT 16
#define CNA_CONV_CON1_ARGB_IN__MASK 0x0000f000
#define CNA_CONV_CON1_ARGB_IN__SHIFT 12
#define CNA_CONV_CON1_RESERVED_2__MASK 0x00000c00
#define CNA_CONV_CON1_RESERVED_2__SHIFT 10
#define CNA_CONV_CON1_PROC_PRECISION__MASK 0x00000380
#define CNA_CONV_CON1_PROC_PRECISION__SHIFT 7
#define CNA_CONV_CON1_IN_PRECISION__MASK 0x00000070
#define CNA_CONV_CON1_IN_PRECISION__SHIFT 4
#define CNA_CONV_CON1_CONV_MODE__MASK 0x0000000f
#define CNA_CONV_CON1_CONV_MODE__SHIFT 0
#define REG_CNA_CONV_CON2 0x00001010
#define CNA_CONV_CON2_RESERVED_0__MASK 0xff000000
#define CNA_CONV_CON2_RESERVED_0__SHIFT 24
#define CNA_CONV_CON2_KERNEL_GROUP__MASK 0x00ff0000
#define CNA_CONV_CON2_KERNEL_GROUP__SHIFT 16
#define CNA_CONV_CON2_RESERVED_1__MASK 0x0000c000
#define CNA_CONV_CON2_RESERVED_1__SHIFT 14
#define CNA_CONV_CON2_FEATURE_GRAINS__MASK 0x00003ff0
#define CNA_CONV_CON2_FEATURE_GRAINS__SHIFT 4
#define CNA_CONV_CON2_RESERVED_2__MASK 0x00000008
#define CNA_CONV_CON2_RESERVED_2__SHIFT 3
#define CNA_CONV_CON2_CSC_WO_EN__MASK 0x00000004
#define CNA_CONV_CON2_CSC_WO_EN__SHIFT 2
#define CNA_CONV_CON2_CSC_DO_EN__MASK 0x00000002
#define CNA_CONV_CON2_CSC_DO_EN__SHIFT 1
#define CNA_CONV_CON2_CMD_FIFO_SRST__MASK 0x00000001
#define CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT 0
#define REG_CNA_CONV_CON3 0x00001014
#define CNA_CONV_CON3_RESERVED_0__MASK 0x80000000
#define CNA_CONV_CON3_RESERVED_0__SHIFT 31
#define CNA_CONV_CON3_NN_MODE__MASK 0x70000000
#define CNA_CONV_CON3_NN_MODE__SHIFT 28
#define CNA_CONV_CON3_RESERVED_1__MASK 0x0c000000
#define CNA_CONV_CON3_RESERVED_1__SHIFT 26
#define CNA_CONV_CON3_ATROUS_Y_DILATION__MASK 0x03e00000
#define CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT 21
#define CNA_CONV_CON3_ATROUS_X_DILATION__MASK 0x001f0000
#define CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT 16
#define CNA_CONV_CON3_RESERVED_2__MASK 0x0000c000
#define CNA_CONV_CON3_RESERVED_2__SHIFT 14
#define CNA_CONV_CON3_DECONV_Y_STRIDE__MASK 0x00003800
#define CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT 11
#define CNA_CONV_CON3_DECONV_X_STRIDE__MASK 0x00000700
#define CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT 8
#define CNA_CONV_CON3_RESERVED_3__MASK 0x000000c0
#define CNA_CONV_CON3_RESERVED_3__SHIFT 6
#define CNA_CONV_CON3_CONV_Y_STRIDE__MASK 0x00000038
#define CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT 3
#define CNA_CONV_CON3_CONV_X_STRIDE__MASK 0x00000007
#define CNA_CONV_CON3_CONV_X_STRIDE__SHIFT 0
#define REG_CNA_DATA_SIZE0 0x00001020
#define CNA_DATA_SIZE0_RESERVED_0__MASK 0xf8000000
#define CNA_DATA_SIZE0_RESERVED_0__SHIFT 27
#define CNA_DATA_SIZE0_DATAIN_WIDTH__MASK 0x07ff0000
#define CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT 16
#define CNA_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
#define CNA_DATA_SIZE0_RESERVED_1__SHIFT 11
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK 0x000007ff
#define CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT 0
#define REG_CNA_DATA_SIZE1 0x00001024
#define CNA_DATA_SIZE1_RESERVED_0__MASK 0xc0000000
#define CNA_DATA_SIZE1_RESERVED_0__SHIFT 30
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK 0x3fff0000
#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT 16
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK 0x0000ffff
#define CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT 0
#define REG_CNA_DATA_SIZE2 0x00001028
#define CNA_DATA_SIZE2_RESERVED_0__MASK 0xfffff800
#define CNA_DATA_SIZE2_RESERVED_0__SHIFT 11
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK 0x000007ff
#define CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT 0
#define REG_CNA_DATA_SIZE3 0x0000102c
#define CNA_DATA_SIZE3_RESERVED_0__MASK 0xff000000
#define CNA_DATA_SIZE3_RESERVED_0__SHIFT 24
#define CNA_DATA_SIZE3_SURF_MODE__MASK 0x00c00000
#define CNA_DATA_SIZE3_SURF_MODE__SHIFT 22
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK 0x003fffff
#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT 0
#define REG_CNA_WEIGHT_SIZE0 0x00001030
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK 0xffffffff
#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT 0
#define REG_CNA_WEIGHT_SIZE1 0x00001034
#define CNA_WEIGHT_SIZE1_RESERVED_0__MASK 0xfff80000
#define CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT 19
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK 0x0007ffff
#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT 0
#define REG_CNA_WEIGHT_SIZE2 0x00001038
#define CNA_WEIGHT_SIZE2_RESERVED_0__MASK 0xe0000000
#define CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT 29
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK 0x1f000000
#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT 24
#define CNA_WEIGHT_SIZE2_RESERVED_1__MASK 0x00e00000
#define CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT 21
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK 0x001f0000
#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT 16
#define CNA_WEIGHT_SIZE2_RESERVED_2__MASK 0x0000c000
#define CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT 14
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK 0x00003fff
#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT 0
#define REG_CNA_CBUF_CON0 0x00001040
#define CNA_CBUF_CON0_RESERVED_0__MASK 0xffffc000
#define CNA_CBUF_CON0_RESERVED_0__SHIFT 14
#define CNA_CBUF_CON0_WEIGHT_REUSE__MASK 0x00002000
#define CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT 13
#define CNA_CBUF_CON0_DATA_REUSE__MASK 0x00001000
#define CNA_CBUF_CON0_DATA_REUSE__SHIFT 12
#define CNA_CBUF_CON0_RESERVED_1__MASK 0x00000800
#define CNA_CBUF_CON0_RESERVED_1__SHIFT 11
#define CNA_CBUF_CON0_FC_DATA_BANK__MASK 0x00000700
#define CNA_CBUF_CON0_FC_DATA_BANK__SHIFT 8
#define CNA_CBUF_CON0_WEIGHT_BANK__MASK 0x000000f0
#define CNA_CBUF_CON0_WEIGHT_BANK__SHIFT 4
#define CNA_CBUF_CON0_DATA_BANK__MASK 0x0000000f
#define CNA_CBUF_CON0_DATA_BANK__SHIFT 0
#define REG_CNA_CBUF_CON1 0x00001044
#define CNA_CBUF_CON1_RESERVED_0__MASK 0xffffc000
#define CNA_CBUF_CON1_RESERVED_0__SHIFT 14
#define CNA_CBUF_CON1_DATA_ENTRIES__MASK 0x00003fff
#define CNA_CBUF_CON1_DATA_ENTRIES__SHIFT 0
#define REG_CNA_CVT_CON0 0x0000104c
#define CNA_CVT_CON0_RESERVED_0__MASK 0xf0000000
#define CNA_CVT_CON0_RESERVED_0__SHIFT 28
#define CNA_CVT_CON0_CVT_TRUNCATE_3__MASK 0x0fc00000
#define CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT 22
#define CNA_CVT_CON0_CVT_TRUNCATE_2__MASK 0x003f0000
#define CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT 16
#define CNA_CVT_CON0_CVT_TRUNCATE_1__MASK 0x0000fc00
#define CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT 10
#define CNA_CVT_CON0_CVT_TRUNCATE_0__MASK 0x000003f0
#define CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT 4
#define CNA_CVT_CON0_DATA_SIGN__MASK 0x00000008
#define CNA_CVT_CON0_DATA_SIGN__SHIFT 3
#define CNA_CVT_CON0_ROUND_TYPE__MASK 0x00000004
#define CNA_CVT_CON0_ROUND_TYPE__SHIFT 2
#define CNA_CVT_CON0_CVT_TYPE__MASK 0x00000002
#define CNA_CVT_CON0_CVT_TYPE__SHIFT 1
#define CNA_CVT_CON0_CVT_BYPASS__MASK 0x00000001
#define CNA_CVT_CON0_CVT_BYPASS__SHIFT 0
#define REG_CNA_CVT_CON1 0x00001050
#define CNA_CVT_CON1_CVT_SCALE0__MASK 0xffff0000
#define CNA_CVT_CON1_CVT_SCALE0__SHIFT 16
#define CNA_CVT_CON1_CVT_OFFSET0__MASK 0x0000ffff
#define CNA_CVT_CON1_CVT_OFFSET0__SHIFT 0
#define REG_CNA_CVT_CON2 0x00001054
#define CNA_CVT_CON2_CVT_SCALE1__MASK 0xffff0000
#define CNA_CVT_CON2_CVT_SCALE1__SHIFT 16
#define CNA_CVT_CON2_CVT_OFFSET1__MASK 0x0000ffff
#define CNA_CVT_CON2_CVT_OFFSET1__SHIFT 0
#define REG_CNA_CVT_CON3 0x00001058
#define CNA_CVT_CON3_CVT_SCALE2__MASK 0xffff0000
#define CNA_CVT_CON3_CVT_SCALE2__SHIFT 16
#define CNA_CVT_CON3_CVT_OFFSET2__MASK 0x0000ffff
#define CNA_CVT_CON3_CVT_OFFSET2__SHIFT 0
#define REG_CNA_CVT_CON4 0x0000105c
#define CNA_CVT_CON4_CVT_SCALE3__MASK 0xffff0000
#define CNA_CVT_CON4_CVT_SCALE3__SHIFT 16
#define CNA_CVT_CON4_CVT_OFFSET3__MASK 0x0000ffff
#define CNA_CVT_CON4_CVT_OFFSET3__SHIFT 0
#define REG_CNA_FC_CON0 0x00001060
#define CNA_FC_CON0_FC_SKIP_DATA__MASK 0xffff0000
#define CNA_FC_CON0_FC_SKIP_DATA__SHIFT 16
#define CNA_FC_CON0_RESERVED_0__MASK 0x0000fffe
#define CNA_FC_CON0_RESERVED_0__SHIFT 1
#define CNA_FC_CON0_FC_SKIP_EN__MASK 0x00000001
#define CNA_FC_CON0_FC_SKIP_EN__SHIFT 0
#define REG_CNA_FC_CON1 0x00001064
#define CNA_FC_CON1_RESERVED_0__MASK 0xfffe0000
#define CNA_FC_CON1_RESERVED_0__SHIFT 17
#define CNA_FC_CON1_DATA_OFFSET__MASK 0x0001ffff
#define CNA_FC_CON1_DATA_OFFSET__SHIFT 0
#define REG_CNA_PAD_CON0 0x00001068
#define CNA_PAD_CON0_RESERVED_0__MASK 0xffffff00
#define CNA_PAD_CON0_RESERVED_0__SHIFT 8
#define CNA_PAD_CON0_PAD_LEFT__MASK 0x000000f0
#define CNA_PAD_CON0_PAD_LEFT__SHIFT 4
#define CNA_PAD_CON0_PAD_TOP__MASK 0x0000000f
#define CNA_PAD_CON0_PAD_TOP__SHIFT 0
#define REG_CNA_FEATURE_DATA_ADDR 0x00001070
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK 0xffffffff
#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT 0
#define REG_CNA_FC_CON2 0x00001074
#define CNA_FC_CON2_RESERVED_0__MASK 0xfffe0000
#define CNA_FC_CON2_RESERVED_0__SHIFT 17
#define CNA_FC_CON2_WEIGHT_OFFSET__MASK 0x0001ffff
#define CNA_FC_CON2_WEIGHT_OFFSET__SHIFT 0
#define REG_CNA_DMA_CON0 0x00001078
#define CNA_DMA_CON0_OV4K_BYPASS__MASK 0x80000000
#define CNA_DMA_CON0_OV4K_BYPASS__SHIFT 31
#define CNA_DMA_CON0_RESERVED_0__MASK 0x7ff00000
#define CNA_DMA_CON0_RESERVED_0__SHIFT 20
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK 0x000f0000
#define CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT 16
#define CNA_DMA_CON0_RESERVED_1__MASK 0x0000fff0
#define CNA_DMA_CON0_RESERVED_1__SHIFT 4
#define CNA_DMA_CON0_DATA_BURST_LEN__MASK 0x0000000f
#define CNA_DMA_CON0_DATA_BURST_LEN__SHIFT 0
#define REG_CNA_DMA_CON1 0x0000107c
#define CNA_DMA_CON1_RESERVED_0__MASK 0xf0000000
#define CNA_DMA_CON1_RESERVED_0__SHIFT 28
#define CNA_DMA_CON1_LINE_STRIDE__MASK 0x0fffffff
#define CNA_DMA_CON1_LINE_STRIDE__SHIFT 0
#define REG_CNA_DMA_CON2 0x00001080
#define CNA_DMA_CON2_RESERVED_0__MASK 0xf0000000
#define CNA_DMA_CON2_RESERVED_0__SHIFT 28
#define CNA_DMA_CON2_SURF_STRIDE__MASK 0x0fffffff
#define CNA_DMA_CON2_SURF_STRIDE__SHIFT 0
#define REG_CNA_FC_DATA_SIZE0 0x00001084
#define CNA_FC_DATA_SIZE0_RESERVED_0__MASK 0xc0000000
#define CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT 30
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK 0x3fff0000
#define CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT 16
#define CNA_FC_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
#define CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT 11
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK 0x000007ff
#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT 0
#define REG_CNA_FC_DATA_SIZE1 0x00001088
#define CNA_FC_DATA_SIZE1_RESERVED_0__MASK 0xffff0000
#define CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT 16
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK 0x0000ffff
#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT 0
#define REG_CNA_CLK_GATE 0x00001090
#define CNA_CLK_GATE_RESERVED_0__MASK 0xffffffe0
#define CNA_CLK_GATE_RESERVED_0__SHIFT 5
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK 0x00000010
#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT 4
#define CNA_CLK_GATE_RESERVED_1__MASK 0x00000008
#define CNA_CLK_GATE_RESERVED_1__SHIFT 3
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK 0x00000004
#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT 2
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK 0x00000002
#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT 1
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK 0x00000001
#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT 0
#define REG_CNA_DCOMP_CTRL 0x00001100
#define CNA_DCOMP_CTRL_RESERVED_0__MASK 0xfffffff0
#define CNA_DCOMP_CTRL_RESERVED_0__SHIFT 4
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK 0x00000008
#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT 3
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK 0x00000007
#define CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT 0
#define REG_CNA_DCOMP_REGNUM 0x00001104
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK 0xffffffff
#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT 0
#define REG_CNA_DCOMP_ADDR0 0x00001110
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK 0xffffffff
#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT0 0x00001140
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT1 0x00001144
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT2 0x00001148
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT3 0x0000114c
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT4 0x00001150
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT5 0x00001154
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT6 0x00001158
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT7 0x0000115c
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT8 0x00001160
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT9 0x00001164
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT10 0x00001168
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT11 0x0000116c
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT12 0x00001170
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT13 0x00001174
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT14 0x00001178
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT 0
#define REG_CNA_DCOMP_AMOUNT15 0x0000117c
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK 0xffffffff
#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT 0
#define REG_CNA_CVT_CON5 0x00001180
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK 0xffffffff
#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT 0
#define REG_CNA_PAD_CON1 0x00001184
#define CNA_PAD_CON1_PAD_VALUE__MASK 0xffffffff
#define CNA_PAD_CON1_PAD_VALUE__SHIFT 0
#define REG_DPU_S_POINTER 0x00004004
#define DPU_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define DPU_S_POINTER_RESERVED_0__SHIFT 17
#define DPU_S_POINTER_EXECUTER__MASK 0x00010000
#define DPU_S_POINTER_EXECUTER__SHIFT 16
#define DPU_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define DPU_S_POINTER_RESERVED_1__SHIFT 6
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define DPU_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define DPU_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define DPU_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define DPU_S_POINTER_POINTER_PP_EN__SHIFT 1
#define DPU_S_POINTER_POINTER__MASK 0x00000001
#define DPU_S_POINTER_POINTER__SHIFT 0
#define REG_DPU_RDMA_RDMA_S_STATUS 0x00005000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK 0xfffc0000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT 18
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK 0x00030000
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT 16
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK 0x0000fffc
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT 2
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK 0x00000003
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_S_POINTER 0x00005004
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT 17
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK 0x00010000
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT 16
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT 6
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT 1
#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK 0x00000001
#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT 0
#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE 0x00005008
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH 0x0000500c
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT 0x00005010
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xe0000000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 29
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK 0x1fff0000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT 16
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x0000e000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL 0x00005014
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR 0x00005018
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_BRDMA_CFG 0x0000501c
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK 0xffffffe0
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT 5
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK 0x0000001e
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT 1
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK 0x00000001
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT 0
#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR 0x00005020
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_NRDMA_CFG 0x00005028
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK 0xffffffe0
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT 5
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK 0x0000001e
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT 1
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK 0x00000001
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT 0
#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR 0x0000502c
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_ERDMA_CFG 0x00005034
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK 0xc0000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT 30
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK 0x20000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT 29
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK 0x10000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT 28
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK 0x0ffffff0
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT 4
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK 0x0000000c
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT 2
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK 0x00000002
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT 1
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK 0x00000001
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR 0x00005038
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE 0x00005040
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK 0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT 4
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG 0x00005044
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK 0xfffc0000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT 18
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK 0x00038000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT 15
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK 0x00007800
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT 11
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK 0x00000700
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT 8
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK 0x000000e0
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT 5
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK 0x00000010
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT 4
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK 0x00000008
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT 3
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000006
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT 1
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG 0x00005048
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK 0xfff80000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT 19
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK 0x0007c000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT 14
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK 0x00002000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT 13
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK 0x00001000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT 12
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK 0x00000e00
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT 9
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK 0x000001c0
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT 6
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK 0x00000038
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT 3
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK 0x00000007
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT 0
#define REG_DPU_RDMA_RDMA_SURF_NOTCH 0x0000504c
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK 0xfffffff0
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT 4
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_PAD_CFG 0x00005064
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK 0xffff0000
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT 16
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK 0x0000ff80
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT 7
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK 0x00000070
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT 4
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK 0x00000008
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT 3
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK 0x00000007
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT 0
#define REG_DPU_RDMA_RDMA_WEIGHT 0x00005068
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK 0xff000000
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT 24
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK 0x00ff0000
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT 16
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK 0x0000ff00
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT 8
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK 0x000000ff
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH 0x0000506c
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK 0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT 4
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT 0
// ============ MESA CNA EMIT (fill_first_regcmd, CNA section) ============
// This is the exact upstream code to port. 'regs' is the output array (util_dynarray);
// EMIT(reg,val) => emit(regs,reg,val) => pack (target<<48)|(val<<16)|reg with target=block+1.
// 'task->' and 'operation->' fields become explicit function parameters in your port.
fill_first_regcmd(struct rkt_ml_subgraph *subgraph,
const struct rkt_operation *operation,
struct util_dynarray *regs, unsigned task_num)
{
struct split_task *task =
util_dynarray_element(&operation->tasks, struct split_task, task_num);
unsigned num_tasks =
util_dynarray_num_elements(&operation->tasks, struct split_task);
unsigned output_zero_point = task->output_zero_point;
unsigned weights_zero_point = task->weights_zero_point;
unsigned offset = output_zero_point - 0x80;
uint32_t con0 = CNA_CBUF_CON0_WEIGHT_BANK(task->weights_banks) |
CNA_CBUF_CON0_DATA_BANK(task->input_banks);
if (task_num > 0 && operation->reuse_weights_cbuf)
con0 |= CNA_CBUF_CON0_WEIGHT_REUSE(1);
EMIT(REG_CNA_CBUF_CON0, con0);
EMIT(REG_CNA_DCOMP_REGNUM, 0);
EMIT(REG_CNA_DCOMP_CTRL, 0);
uint32_t con1 = 0x0;
if (task->input_channels_real == 1) {
con1 |= CNA_CONV_CON1_NONALIGN_DMA(1) | CNA_CONV_CON1_GROUP_LINE_OFF(1) |
CNA_CONV_CON1_ARGB_IN(8);
}
if (operation->depthwise)
con1 |= CNA_CONV_CON1_CONV_MODE(3);
EMIT(REG_CNA_CONV_CON1, con1);
EMIT(REG_DPU_S_POINTER, DPU_S_POINTER_POINTER_PP_MODE(1) |
DPU_S_POINTER_EXECUTER_PP_EN(1) |
DPU_S_POINTER_POINTER_PP_EN(1));
EMIT(REG_DPU_RDMA_RDMA_S_POINTER,
DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(1) |
DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(1) |
DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(1));
EMIT(REG_CNA_CONV_CON1, con1);
EMIT(REG_CNA_CONV_CON2,
CNA_CONV_CON2_FEATURE_GRAINS(
50 + task->stride_y + 1)); /* Magic: Seems to pass the most tests */
EMIT(REG_CNA_CONV_CON3, CNA_CONV_CON3_CONV_X_STRIDE(task->stride_x) |
CNA_CONV_CON3_CONV_Y_STRIDE(task->stride_y));
EMIT(REG_CNA_DATA_SIZE0,
CNA_DATA_SIZE0_DATAIN_WIDTH(task->input_width) |
CNA_DATA_SIZE0_DATAIN_HEIGHT(task->input_height));
EMIT(REG_CNA_DATA_SIZE1,
CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL(task->input_channels_real - 1) |
CNA_DATA_SIZE1_DATAIN_CHANNEL(task->input_channels));
EMIT(REG_CNA_DATA_SIZE2, CNA_DATA_SIZE2_DATAOUT_WIDTH(task->output_width));
EMIT(REG_CNA_DATA_SIZE3, CNA_DATA_SIZE3_DATAOUT_ATOMICS(task->atomic_count));
EMIT(REG_CNA_WEIGHT_SIZE0, task->weights_width * task->weights_height *
task->input_channels * task->weights_kernels);
EMIT(REG_CNA_WEIGHT_SIZE1,
task->weights_width * task->weights_height * task->input_channels);
EMIT(REG_CNA_WEIGHT_SIZE2,
CNA_WEIGHT_SIZE2_WEIGHT_WIDTH(task->weights_width) |
CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT(task->weights_height) |
CNA_WEIGHT_SIZE2_WEIGHT_KERNELS(task->weights_kernels));
EMIT(REG_CNA_CBUF_CON0, con0);
EMIT(REG_CNA_CBUF_CON1, CNA_CBUF_CON1_DATA_ENTRIES(task->input_data_entries));
if (task->input_channels_real == 1) {
unsigned truncate = 14;
unsigned scale = 16384;
unsigned offset = 65408;
if (operation->addition_input || operation->add_tensor != -1) {
truncate = 15;
scale = 32388;
}
EMIT(REG_CNA_CVT_CON0, CNA_CVT_CON0_CVT_TRUNCATE_3(truncate) |
CNA_CVT_CON0_CVT_TRUNCATE_2(truncate) |
CNA_CVT_CON0_CVT_TRUNCATE_1(truncate) |
CNA_CVT_CON0_CVT_TRUNCATE_0(truncate));
EMIT(REG_CNA_CVT_CON1,
CNA_CVT_CON1_CVT_SCALE0(scale) | CNA_CVT_CON1_CVT_OFFSET0(offset));
EMIT(REG_CNA_CVT_CON2,
CNA_CVT_CON2_CVT_SCALE1(scale) | CNA_CVT_CON2_CVT_OFFSET1(offset));
EMIT(REG_CNA_CVT_CON3,
CNA_CVT_CON3_CVT_SCALE2(scale) | CNA_CVT_CON3_CVT_OFFSET2(offset));
EMIT(REG_CNA_CVT_CON4,
CNA_CVT_CON4_CVT_SCALE3(scale) | CNA_CVT_CON4_CVT_OFFSET3(offset));
} else {
EMIT(REG_CNA_CVT_CON0, CNA_CVT_CON0_DATA_SIGN(1) |
CNA_CVT_CON0_CVT_TYPE(1) |
CNA_CVT_CON0_CVT_BYPASS(1));
EMIT(REG_CNA_CVT_CON1, CNA_CVT_CON1_CVT_SCALE0(1));
EMIT(REG_CNA_CVT_CON2, CNA_CVT_CON2_CVT_SCALE1(1));
EMIT(REG_CNA_CVT_CON3, CNA_CVT_CON3_CVT_SCALE2(1));
EMIT(REG_CNA_CVT_CON4, CNA_CVT_CON4_CVT_SCALE3(1));
}
EMIT(REG_CNA_FC_CON0, 0);
EMIT(REG_CNA_FC_CON1, 0);
EMIT(REG_CNA_PAD_CON0, CNA_PAD_CON0_PAD_LEFT(task->pad_left) |
CNA_PAD_CON0_PAD_TOP(task->pad_top));
EMIT(REG_CNA_FEATURE_DATA_ADDR,
rkt_get_tensor(subgraph, operation->input_index)->phys_addr +
task->input_offset);
EMIT(REG_CNA_FC_CON2, 0);
EMIT(REG_CNA_DMA_CON0,
CNA_DMA_CON0_WEIGHT_BURST_LEN(15) | CNA_DMA_CON0_DATA_BURST_LEN(15));
EMIT(REG_CNA_DMA_CON1, CNA_DMA_CON1_LINE_STRIDE(task->input_line_stride));
EMIT(REG_CNA_DMA_CON2, CNA_DMA_CON2_SURF_STRIDE(task->input_surface_stride));
EMIT(REG_CNA_FC_DATA_SIZE0,
CNA_FC_DATA_SIZE0_DMA_WIDTH(operation->input_width) |
CNA_FC_DATA_SIZE0_DMA_HEIGHT(task->input_height));
EMIT(REG_CNA_FC_DATA_SIZE1,
CNA_FC_DATA_SIZE1_DMA_CHANNEL(task->input_channels));
EMIT(REG_CNA_DCOMP_CTRL, 0);
EMIT(REG_CNA_DCOMP_REGNUM, 0);
EMIT(REG_CNA_DCOMP_ADDR0, rkt_resource(operation->weights)->phys_addr);
EMIT(REG_CNA_DCOMP_AMOUNT0, 0);
EMIT(REG_CNA_DCOMP_AMOUNT1, 0);
EMIT(REG_CNA_DCOMP_AMOUNT2, 0);
EMIT(REG_CNA_DCOMP_AMOUNT3, 0);
EMIT(REG_CNA_DCOMP_AMOUNT4, 0);
EMIT(REG_CNA_DCOMP_AMOUNT5, 0);
EMIT(REG_CNA_DCOMP_AMOUNT6, 0);
EMIT(REG_CNA_DCOMP_AMOUNT7, 0);
EMIT(REG_CNA_DCOMP_AMOUNT8, 0);
EMIT(REG_CNA_DCOMP_AMOUNT9, 0);
EMIT(REG_CNA_DCOMP_AMOUNT10, 0);
EMIT(REG_CNA_DCOMP_AMOUNT11, 0);
EMIT(REG_CNA_DCOMP_AMOUNT12, 0);
EMIT(REG_CNA_DCOMP_AMOUNT13, 0);
EMIT(REG_CNA_DCOMP_AMOUNT14, 0);
EMIT(REG_CNA_DCOMP_AMOUNT15, 0);
if (task->input_channels_real == 1) {
EMIT(REG_CNA_CVT_CON5, 65535);
} else {
EMIT(REG_CNA_CVT_CON5, 0);
}
int32_t pad_con1;
if (task->weights_width >= 3 && task->input_zero_point == 0x0)
pad_con1 = 0xffff8080;
else
pad_con1 = task->input_zero_point - 0x80;
if (operation->addition_input || operation->add_tensor != -1)
pad_con1 = 0xffffff80;
if (operation->depthwise && task->input_zero_point == 0x8b)
pad_con1 = 0x0b0b;
EMIT(REG_CNA_PAD_CON1, pad_con1);
uint32_t misc_cfg = CORE_MISC_CFG_QD_EN(1);
if (operation->depthwise)
misc_cfg |= CORE_MISC_CFG_DW_EN(1);
userspace/npu-probe/coredpu_defs.h
+769
View File
@@ -0,0 +1,769 @@
#ifndef COREDPU_DEFS_H
#define COREDPU_DEFS_H
#define REG_PC_VERSION 0x00000000
#define PC_VERSION_VERSION__MASK 0xffffffff
#define PC_VERSION_VERSION__SHIFT 0
#define REG_PC_VERSION_NUM 0x00000004
#define PC_VERSION_NUM_VERSION_NUM__MASK 0xffffffff
#define PC_VERSION_NUM_VERSION_NUM__SHIFT 0
#define REG_PC_OPERATION_ENABLE 0x00000008
#define PC_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define PC_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define PC_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define PC_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_PC_BASE_ADDRESS 0x00000010
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK 0xfffffff0
#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT 4
#define PC_BASE_ADDRESS_RESERVED_0__MASK 0x0000000e
#define PC_BASE_ADDRESS_RESERVED_0__SHIFT 1
#define PC_BASE_ADDRESS_PC_SEL__MASK 0x00000001
#define PC_BASE_ADDRESS_PC_SEL__SHIFT 0
#define REG_PC_REGISTER_AMOUNTS 0x00000014
#define PC_REGISTER_AMOUNTS_RESERVED_0__MASK 0xffff0000
#define PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT 16
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK 0x0000ffff
#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT 0
#define REG_PC_INTERRUPT_MASK 0x00000020
#define PC_INTERRUPT_MASK_RESERVED_0__MASK 0xffffc000
#define PC_INTERRUPT_MASK_RESERVED_0__SHIFT 14
#define PC_INTERRUPT_MASK_DMA_WRITE_ERROR 0x00002000
#define PC_INTERRUPT_MASK_DMA_READ_ERROR 0x00001000
#define PC_INTERRUPT_MASK_PPU_1 0x00000800
#define PC_INTERRUPT_MASK_PPU_0 0x00000400
#define PC_INTERRUPT_MASK_DPU_1 0x00000200
#define PC_INTERRUPT_MASK_DPU_0 0x00000100
#define PC_INTERRUPT_MASK_CORE_1 0x00000080
#define PC_INTERRUPT_MASK_CORE_0 0x00000040
#define PC_INTERRUPT_MASK_CNA_CSC_1 0x00000020
#define PC_INTERRUPT_MASK_CNA_CSC_0 0x00000010
#define PC_INTERRUPT_MASK_CNA_WEIGHT_1 0x00000008
#define PC_INTERRUPT_MASK_CNA_WEIGHT_0 0x00000004
#define PC_INTERRUPT_MASK_CNA_FEATURE_1 0x00000002
#define PC_INTERRUPT_MASK_CNA_FEATURE_0 0x00000001
#define REG_PC_INTERRUPT_CLEAR 0x00000024
#define PC_INTERRUPT_CLEAR_RESERVED_0__MASK 0xffffc000
#define PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT 14
#define PC_INTERRUPT_CLEAR_DMA_WRITE_ERROR 0x00002000
#define PC_INTERRUPT_CLEAR_DMA_READ_ERROR 0x00001000
#define PC_INTERRUPT_CLEAR_PPU_1 0x00000800
#define PC_INTERRUPT_CLEAR_PPU_0 0x00000400
#define PC_INTERRUPT_CLEAR_DPU_1 0x00000200
#define PC_INTERRUPT_CLEAR_DPU_0 0x00000100
#define PC_INTERRUPT_CLEAR_CORE_1 0x00000080
#define PC_INTERRUPT_CLEAR_CORE_0 0x00000040
#define PC_INTERRUPT_CLEAR_CNA_CSC_1 0x00000020
#define PC_INTERRUPT_CLEAR_CNA_CSC_0 0x00000010
#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_1 0x00000008
#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_0 0x00000004
#define PC_INTERRUPT_CLEAR_CNA_FEATURE_1 0x00000002
#define PC_INTERRUPT_CLEAR_CNA_FEATURE_0 0x00000001
#define REG_PC_INTERRUPT_STATUS 0x00000028
#define PC_INTERRUPT_STATUS_RESERVED_0__MASK 0xffffc000
#define PC_INTERRUPT_STATUS_RESERVED_0__SHIFT 14
#define PC_INTERRUPT_STATUS_DMA_WRITE_ERROR 0x00002000
#define PC_INTERRUPT_STATUS_DMA_READ_ERROR 0x00001000
#define PC_INTERRUPT_STATUS_PPU_1 0x00000800
#define PC_INTERRUPT_STATUS_PPU_0 0x00000400
#define PC_INTERRUPT_STATUS_DPU_1 0x00000200
#define PC_INTERRUPT_STATUS_DPU_0 0x00000100
#define PC_INTERRUPT_STATUS_CORE_1 0x00000080
#define PC_INTERRUPT_STATUS_CORE_0 0x00000040
#define PC_INTERRUPT_STATUS_CNA_CSC_1 0x00000020
#define PC_INTERRUPT_STATUS_CNA_CSC_0 0x00000010
#define PC_INTERRUPT_STATUS_CNA_WEIGHT_1 0x00000008
#define PC_INTERRUPT_STATUS_CNA_WEIGHT_0 0x00000004
#define PC_INTERRUPT_STATUS_CNA_FEATURE_1 0x00000002
#define PC_INTERRUPT_STATUS_CNA_FEATURE_0 0x00000001
#define REG_PC_INTERRUPT_RAW_STATUS 0x0000002c
#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK 0xffffc000
#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT 14
#define PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR 0x00002000
#define PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR 0x00001000
#define PC_INTERRUPT_RAW_STATUS_PPU_1 0x00000800
#define PC_INTERRUPT_RAW_STATUS_PPU_0 0x00000400
#define PC_INTERRUPT_RAW_STATUS_DPU_1 0x00000200
#define PC_INTERRUPT_RAW_STATUS_DPU_0 0x00000100
#define PC_INTERRUPT_RAW_STATUS_CORE_1 0x00000080
#define PC_INTERRUPT_RAW_STATUS_CORE_0 0x00000040
#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_1 0x00000020
#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_0 0x00000010
#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_1 0x00000008
#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_0 0x00000004
#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_1 0x00000002
#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_0 0x00000001
#define REG_PC_TASK_CON 0x00000030
#define PC_TASK_CON_RESERVED_0__MASK 0xffffc000
#define PC_TASK_CON_RESERVED_0__SHIFT 14
#define PC_TASK_CON_TASK_COUNT_CLEAR__MASK 0x00002000
#define PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT 13
#define PC_TASK_CON_TASK_PP_EN__MASK 0x00001000
#define PC_TASK_CON_TASK_PP_EN__SHIFT 12
#define PC_TASK_CON_TASK_NUMBER__MASK 0x00000fff
#define PC_TASK_CON_TASK_NUMBER__SHIFT 0
#define REG_PC_TASK_DMA_BASE_ADDR 0x00000034
#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK 0xfffffff0
#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT 4
#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK 0x0000000f
#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT 0
#define REG_PC_TASK_STATUS 0x0000003c
#define PC_TASK_STATUS_RESERVED_0__MASK 0xf0000000
#define PC_TASK_STATUS_RESERVED_0__SHIFT 28
#define PC_TASK_STATUS_TASK_STATUS__MASK 0x0fffffff
#define PC_TASK_STATUS_TASK_STATUS__SHIFT 0
#define REG_CORE_S_STATUS 0x00003000
#define CORE_S_STATUS_RESERVED_0__MASK 0xfffc0000
#define CORE_S_STATUS_RESERVED_0__SHIFT 18
#define CORE_S_STATUS_STATUS_1__MASK 0x00030000
#define CORE_S_STATUS_STATUS_1__SHIFT 16
#define CORE_S_STATUS_RESERVED_1__MASK 0x0000fffc
#define CORE_S_STATUS_RESERVED_1__SHIFT 2
#define CORE_S_STATUS_STATUS_0__MASK 0x00000003
#define CORE_S_STATUS_STATUS_0__SHIFT 0
#define REG_CORE_S_POINTER 0x00003004
#define CORE_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define CORE_S_POINTER_RESERVED_0__SHIFT 17
#define CORE_S_POINTER_EXECUTER__MASK 0x00010000
#define CORE_S_POINTER_EXECUTER__SHIFT 16
#define CORE_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define CORE_S_POINTER_RESERVED_1__SHIFT 6
#define CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define CORE_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define CORE_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define CORE_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define CORE_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define CORE_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define CORE_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define CORE_S_POINTER_POINTER_PP_EN__SHIFT 1
#define CORE_S_POINTER_POINTER__MASK 0x00000001
#define CORE_S_POINTER_POINTER__SHIFT 0
#define REG_CORE_OPERATION_ENABLE 0x00003008
#define CORE_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define CORE_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define CORE_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define CORE_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_CORE_MAC_GATING 0x0000300c
#define CORE_MAC_GATING_RESERVED_0__MASK 0xf8000000
#define CORE_MAC_GATING_RESERVED_0__SHIFT 27
#define CORE_MAC_GATING_SLCG_OP_EN__MASK 0x07ffffff
#define CORE_MAC_GATING_SLCG_OP_EN__SHIFT 0
#define REG_CORE_MISC_CFG 0x00003010
#define CORE_MISC_CFG_RESERVED_0__MASK 0xfff00000
#define CORE_MISC_CFG_RESERVED_0__SHIFT 20
#define CORE_MISC_CFG_SOFT_GATING__MASK 0x000fc000
#define CORE_MISC_CFG_SOFT_GATING__SHIFT 14
#define CORE_MISC_CFG_RESERVED_1__MASK 0x00003800
#define CORE_MISC_CFG_RESERVED_1__SHIFT 11
#define CORE_MISC_CFG_PROC_PRECISION__MASK 0x00000700
#define CORE_MISC_CFG_PROC_PRECISION__SHIFT 8
#define CORE_MISC_CFG_RESERVED_2__MASK 0x000000fc
#define CORE_MISC_CFG_RESERVED_2__SHIFT 2
#define CORE_MISC_CFG_DW_EN__MASK 0x00000002
#define CORE_MISC_CFG_DW_EN__SHIFT 1
#define CORE_MISC_CFG_QD_EN__MASK 0x00000001
#define CORE_MISC_CFG_QD_EN__SHIFT 0
#define REG_CORE_DATAOUT_SIZE_0 0x00003014
#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK 0xffff0000
#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT 16
#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK 0x0000ffff
#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT 0
#define REG_CORE_DATAOUT_SIZE_1 0x00003018
#define CORE_DATAOUT_SIZE_1_RESERVED_0__MASK 0xffff0000
#define CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT 16
#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK 0x0000ffff
#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT 0
#define REG_CORE_CLIP_TRUNCATE 0x0000301c
#define CORE_CLIP_TRUNCATE_RESERVED_0__MASK 0xffffff80
#define CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT 7
#define CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK 0x00000040
#define CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT 6
#define CORE_CLIP_TRUNCATE_RESERVED_1__MASK 0x00000020
#define CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT 5
#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK 0x0000001f
#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT 0
#define REG_DPU_S_STATUS 0x00004000
#define DPU_S_STATUS_RESERVED_0__MASK 0xfffc0000
#define DPU_S_STATUS_RESERVED_0__SHIFT 18
#define DPU_S_STATUS_STATUS_1__MASK 0x00030000
#define DPU_S_STATUS_STATUS_1__SHIFT 16
#define DPU_S_STATUS_RESERVED_1__MASK 0x0000fffc
#define DPU_S_STATUS_RESERVED_1__SHIFT 2
#define DPU_S_STATUS_STATUS_0__MASK 0x00000003
#define DPU_S_STATUS_STATUS_0__SHIFT 0
#define REG_DPU_S_POINTER 0x00004004
#define DPU_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define DPU_S_POINTER_RESERVED_0__SHIFT 17
#define DPU_S_POINTER_EXECUTER__MASK 0x00010000
#define DPU_S_POINTER_EXECUTER__SHIFT 16
#define DPU_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define DPU_S_POINTER_RESERVED_1__SHIFT 6
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define DPU_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define DPU_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define DPU_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define DPU_S_POINTER_POINTER_PP_EN__SHIFT 1
#define DPU_S_POINTER_POINTER__MASK 0x00000001
#define DPU_S_POINTER_POINTER__SHIFT 0
#define REG_DPU_OPERATION_ENABLE 0x00004008
#define DPU_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define DPU_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define DPU_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define DPU_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_DPU_FEATURE_MODE_CFG 0x0000400c
#define DPU_FEATURE_MODE_CFG_COMB_USE__MASK 0x80000000
#define DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT 31
#define DPU_FEATURE_MODE_CFG_TP_EN__MASK 0x40000000
#define DPU_FEATURE_MODE_CFG_TP_EN__SHIFT 30
#define DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK 0x3c000000
#define DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT 26
#define DPU_FEATURE_MODE_CFG_NONALIGN__MASK 0x02000000
#define DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT 25
#define DPU_FEATURE_MODE_CFG_SURF_LEN__MASK 0x01fffe00
#define DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT 9
#define DPU_FEATURE_MODE_CFG_BURST_LEN__MASK 0x000001e0
#define DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT 5
#define DPU_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000018
#define DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT 3
#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK 0x00000006
#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT 1
#define DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
#define DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
#define REG_DPU_DATA_FORMAT 0x00004010
#define DPU_DATA_FORMAT_OUT_PRECISION__MASK 0xe0000000
#define DPU_DATA_FORMAT_OUT_PRECISION__SHIFT 29
#define DPU_DATA_FORMAT_IN_PRECISION__MASK 0x1c000000
#define DPU_DATA_FORMAT_IN_PRECISION__SHIFT 26
#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK 0x03ff0000
#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT 16
#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK 0x0000fc00
#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT 10
#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK 0x000003f0
#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT 4
#define DPU_DATA_FORMAT_MC_SURF_OUT__MASK 0x00000008
#define DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT 3
#define DPU_DATA_FORMAT_PROC_PRECISION__MASK 0x00000007
#define DPU_DATA_FORMAT_PROC_PRECISION__SHIFT 0
#define REG_DPU_OFFSET_PEND 0x00004014
#define DPU_OFFSET_PEND_RESERVED_0__MASK 0xffff0000
#define DPU_OFFSET_PEND_RESERVED_0__SHIFT 16
#define DPU_OFFSET_PEND_OFFSET_PEND__MASK 0x0000ffff
#define DPU_OFFSET_PEND_OFFSET_PEND__SHIFT 0
#define REG_DPU_DST_BASE_ADDR 0x00004020
#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK 0xffffffff
#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT 0
#define REG_DPU_DST_SURF_STRIDE 0x00004024
#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK 0xfffffff0
#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT 4
#define DPU_DST_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
#define DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT 0
#define REG_DPU_DATA_CUBE_WIDTH 0x00004030
#define DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
#define DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
#define DPU_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
#define DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
#define REG_DPU_DATA_CUBE_HEIGHT 0x00004034
#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xfe000000
#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 25
#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK 0x01c00000
#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT 22
#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x003fe000
#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
#define DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
#define DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
#define REG_DPU_DATA_CUBE_NOTCH_ADDR 0x00004038
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK 0xe0000000
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT 29
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK 0x1fff0000
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT 16
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK 0x0000e000
#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT 13
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK 0x00001fff
#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT 0
#define REG_DPU_DATA_CUBE_CHANNEL 0x0000403c
#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xe0000000
#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 29
#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK 0x1fff0000
#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT 16
#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK 0x0000e000
#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT 13
#define DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
#define DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
#define REG_DPU_BS_CFG 0x00004040
#define DPU_BS_CFG_RESERVED_0__MASK 0xfff00000
#define DPU_BS_CFG_RESERVED_0__SHIFT 20
#define DPU_BS_CFG_BS_ALU_ALGO__MASK 0x000f0000
#define DPU_BS_CFG_BS_ALU_ALGO__SHIFT 16
#define DPU_BS_CFG_RESERVED_1__MASK 0x0000fe00
#define DPU_BS_CFG_RESERVED_1__SHIFT 9
#define DPU_BS_CFG_BS_ALU_SRC__MASK 0x00000100
#define DPU_BS_CFG_BS_ALU_SRC__SHIFT 8
#define DPU_BS_CFG_BS_RELUX_EN__MASK 0x00000080
#define DPU_BS_CFG_BS_RELUX_EN__SHIFT 7
#define DPU_BS_CFG_BS_RELU_BYPASS__MASK 0x00000040
#define DPU_BS_CFG_BS_RELU_BYPASS__SHIFT 6
#define DPU_BS_CFG_BS_MUL_PRELU__MASK 0x00000020
#define DPU_BS_CFG_BS_MUL_PRELU__SHIFT 5
#define DPU_BS_CFG_BS_MUL_BYPASS__MASK 0x00000010
#define DPU_BS_CFG_BS_MUL_BYPASS__SHIFT 4
#define DPU_BS_CFG_RESERVED_2__MASK 0x0000000c
#define DPU_BS_CFG_RESERVED_2__SHIFT 2
#define DPU_BS_CFG_BS_ALU_BYPASS__MASK 0x00000002
#define DPU_BS_CFG_BS_ALU_BYPASS__SHIFT 1
#define DPU_BS_CFG_BS_BYPASS__MASK 0x00000001
#define DPU_BS_CFG_BS_BYPASS__SHIFT 0
#define REG_DPU_BS_ALU_CFG 0x00004044
#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK 0xffffffff
#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT 0
#define REG_DPU_BS_MUL_CFG 0x00004048
#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK 0xffff0000
#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT 16
#define DPU_BS_MUL_CFG_RESERVED_0__MASK 0x0000c000
#define DPU_BS_MUL_CFG_RESERVED_0__SHIFT 14
#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK 0x00003f00
#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT 8
#define DPU_BS_MUL_CFG_RESERVED_1__MASK 0x000000fc
#define DPU_BS_MUL_CFG_RESERVED_1__SHIFT 2
#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK 0x00000002
#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT 1
#define DPU_BS_MUL_CFG_BS_MUL_SRC__MASK 0x00000001
#define DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT 0
#define REG_DPU_BS_RELUX_CMP_VALUE 0x0000404c
#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK 0xffffffff
#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT 0
#define REG_DPU_BS_OW_CFG 0x00004050
#define DPU_BS_OW_CFG_RGP_CNTER__MASK 0xf0000000
#define DPU_BS_OW_CFG_RGP_CNTER__SHIFT 28
#define DPU_BS_OW_CFG_TP_ORG_EN__MASK 0x08000000
#define DPU_BS_OW_CFG_TP_ORG_EN__SHIFT 27
#define DPU_BS_OW_CFG_RESERVED_0__MASK 0x07fff800
#define DPU_BS_OW_CFG_RESERVED_0__SHIFT 11
#define DPU_BS_OW_CFG_SIZE_E_2__MASK 0x00000700
#define DPU_BS_OW_CFG_SIZE_E_2__SHIFT 8
#define DPU_BS_OW_CFG_SIZE_E_1__MASK 0x000000e0
#define DPU_BS_OW_CFG_SIZE_E_1__SHIFT 5
#define DPU_BS_OW_CFG_SIZE_E_0__MASK 0x0000001c
#define DPU_BS_OW_CFG_SIZE_E_0__SHIFT 2
#define DPU_BS_OW_CFG_OD_BYPASS__MASK 0x00000002
#define DPU_BS_OW_CFG_OD_BYPASS__SHIFT 1
#define DPU_BS_OW_CFG_OW_SRC__MASK 0x00000001
#define DPU_BS_OW_CFG_OW_SRC__SHIFT 0
#define REG_DPU_BS_OW_OP 0x00004054
#define DPU_BS_OW_OP_RESERVED_0__MASK 0xffff0000
#define DPU_BS_OW_OP_RESERVED_0__SHIFT 16
#define DPU_BS_OW_OP_OW_OP__MASK 0x0000ffff
#define DPU_BS_OW_OP_OW_OP__SHIFT 0
#define REG_DPU_WDMA_SIZE_0 0x00004058
#define DPU_WDMA_SIZE_0_RESERVED_0__MASK 0xf0000000
#define DPU_WDMA_SIZE_0_RESERVED_0__SHIFT 28
#define DPU_WDMA_SIZE_0_TP_PRECISION__MASK 0x08000000
#define DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT 27
#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK 0x07ff0000
#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT 16
#define DPU_WDMA_SIZE_0_RESERVED_1__MASK 0x0000e000
#define DPU_WDMA_SIZE_0_RESERVED_1__SHIFT 13
#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK 0x00001fff
#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT 0
#define REG_DPU_WDMA_SIZE_1 0x0000405c
#define DPU_WDMA_SIZE_1_RESERVED_0__MASK 0xe0000000
#define DPU_WDMA_SIZE_1_RESERVED_0__SHIFT 29
#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK 0x1fff0000
#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT 16
#define DPU_WDMA_SIZE_1_RESERVED_1__MASK 0x0000e000
#define DPU_WDMA_SIZE_1_RESERVED_1__SHIFT 13
#define DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK 0x00001fff
#define DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT 0
#define REG_DPU_BN_CFG 0x00004060
#define DPU_BN_CFG_RESERVED_0__MASK 0xfff00000
#define DPU_BN_CFG_RESERVED_0__SHIFT 20
#define DPU_BN_CFG_BN_ALU_ALGO__MASK 0x000f0000
#define DPU_BN_CFG_BN_ALU_ALGO__SHIFT 16
#define DPU_BN_CFG_RESERVED_1__MASK 0x0000fe00
#define DPU_BN_CFG_RESERVED_1__SHIFT 9
#define DPU_BN_CFG_BN_ALU_SRC__MASK 0x00000100
#define DPU_BN_CFG_BN_ALU_SRC__SHIFT 8
#define DPU_BN_CFG_BN_RELUX_EN__MASK 0x00000080
#define DPU_BN_CFG_BN_RELUX_EN__SHIFT 7
#define DPU_BN_CFG_BN_RELU_BYPASS__MASK 0x00000040
#define DPU_BN_CFG_BN_RELU_BYPASS__SHIFT 6
#define DPU_BN_CFG_BN_MUL_PRELU__MASK 0x00000020
#define DPU_BN_CFG_BN_MUL_PRELU__SHIFT 5
#define DPU_BN_CFG_BN_MUL_BYPASS__MASK 0x00000010
#define DPU_BN_CFG_BN_MUL_BYPASS__SHIFT 4
#define DPU_BN_CFG_RESERVED_2__MASK 0x0000000c
#define DPU_BN_CFG_RESERVED_2__SHIFT 2
#define DPU_BN_CFG_BN_ALU_BYPASS__MASK 0x00000002
#define DPU_BN_CFG_BN_ALU_BYPASS__SHIFT 1
#define DPU_BN_CFG_BN_BYPASS__MASK 0x00000001
#define DPU_BN_CFG_BN_BYPASS__SHIFT 0
#define REG_DPU_BN_ALU_CFG 0x00004064
#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK 0xffffffff
#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT 0
#define REG_DPU_BN_MUL_CFG 0x00004068
#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK 0xffff0000
#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT 16
#define DPU_BN_MUL_CFG_RESERVED_0__MASK 0x0000c000
#define DPU_BN_MUL_CFG_RESERVED_0__SHIFT 14
#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK 0x00003f00
#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT 8
#define DPU_BN_MUL_CFG_RESERVED_1__MASK 0x000000fc
#define DPU_BN_MUL_CFG_RESERVED_1__SHIFT 2
#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK 0x00000002
#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT 1
#define DPU_BN_MUL_CFG_BN_MUL_SRC__MASK 0x00000001
#define DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT 0
#define REG_DPU_BN_RELUX_CMP_VALUE 0x0000406c
#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK 0xffffffff
#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT 0
#define REG_DPU_EW_CFG 0x00004070
#define DPU_EW_CFG_EW_CVT_TYPE__MASK 0x80000000
#define DPU_EW_CFG_EW_CVT_TYPE__SHIFT 31
#define DPU_EW_CFG_EW_CVT_ROUND__MASK 0x40000000
#define DPU_EW_CFG_EW_CVT_ROUND__SHIFT 30
#define DPU_EW_CFG_EW_DATA_MODE__MASK 0x30000000
#define DPU_EW_CFG_EW_DATA_MODE__SHIFT 28
#define DPU_EW_CFG_RESERVED_0__MASK 0x0f000000
#define DPU_EW_CFG_RESERVED_0__SHIFT 24
#define DPU_EW_CFG_EDATA_SIZE__MASK 0x00c00000
#define DPU_EW_CFG_EDATA_SIZE__SHIFT 22
#define DPU_EW_CFG_EW_EQUAL_EN__MASK 0x00200000
#define DPU_EW_CFG_EW_EQUAL_EN__SHIFT 21
#define DPU_EW_CFG_EW_BINARY_EN__MASK 0x00100000
#define DPU_EW_CFG_EW_BINARY_EN__SHIFT 20
#define DPU_EW_CFG_EW_ALU_ALGO__MASK 0x000f0000
#define DPU_EW_CFG_EW_ALU_ALGO__SHIFT 16
#define DPU_EW_CFG_RESERVED_1__MASK 0x0000f800
#define DPU_EW_CFG_RESERVED_1__SHIFT 11
#define DPU_EW_CFG_EW_RELUX_EN__MASK 0x00000400
#define DPU_EW_CFG_EW_RELUX_EN__SHIFT 10
#define DPU_EW_CFG_EW_RELU_BYPASS__MASK 0x00000200
#define DPU_EW_CFG_EW_RELU_BYPASS__SHIFT 9
#define DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK 0x00000100
#define DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT 8
#define DPU_EW_CFG_EW_LUT_BYPASS__MASK 0x00000080
#define DPU_EW_CFG_EW_LUT_BYPASS__SHIFT 7
#define DPU_EW_CFG_EW_OP_SRC__MASK 0x00000040
#define DPU_EW_CFG_EW_OP_SRC__SHIFT 6
#define DPU_EW_CFG_EW_MUL_PRELU__MASK 0x00000020
#define DPU_EW_CFG_EW_MUL_PRELU__SHIFT 5
#define DPU_EW_CFG_RESERVED_2__MASK 0x00000018
#define DPU_EW_CFG_RESERVED_2__SHIFT 3
#define DPU_EW_CFG_EW_OP_TYPE__MASK 0x00000004
#define DPU_EW_CFG_EW_OP_TYPE__SHIFT 2
#define DPU_EW_CFG_EW_OP_BYPASS__MASK 0x00000002
#define DPU_EW_CFG_EW_OP_BYPASS__SHIFT 1
#define DPU_EW_CFG_EW_BYPASS__MASK 0x00000001
#define DPU_EW_CFG_EW_BYPASS__SHIFT 0
#define REG_DPU_EW_CVT_OFFSET_VALUE 0x00004074
#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK 0xffffffff
#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT 0
#define REG_DPU_EW_CVT_SCALE_VALUE 0x00004078
#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK 0xffc00000
#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT 22
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK 0x003f0000
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT 16
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK 0x0000ffff
#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT 0
#define REG_DPU_EW_RELUX_CMP_VALUE 0x0000407c
#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK 0xffffffff
#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT 0
#define REG_DPU_OUT_CVT_OFFSET 0x00004080
#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK 0xffffffff
#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT 0
#define REG_DPU_OUT_CVT_SCALE 0x00004084
#define DPU_OUT_CVT_SCALE_RESERVED_0__MASK 0xfffe0000
#define DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT 17
#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK 0x00010000
#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT 16
#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK 0x0000ffff
#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT 0
#define REG_DPU_OUT_CVT_SHIFT 0x00004088
#define DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK 0x80000000
#define DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT 31
#define DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK 0x40000000
#define DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT 30
#define DPU_OUT_CVT_SHIFT_RESERVED_0__MASK 0x3ff00000
#define DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT 20
#define DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK 0x000ff000
#define DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT 12
#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK 0x00000fff
#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT 0
#define REG_DPU_EW_OP_VALUE_0 0x00004090
#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK 0xffffffff
#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT 0
#define REG_DPU_EW_OP_VALUE_1 0x00004094
#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK 0xffffffff
#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT 0
#define REG_DPU_EW_OP_VALUE_2 0x00004098
#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK 0xffffffff
#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT 0
#define REG_DPU_EW_OP_VALUE_3 0x0000409c
#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK 0xffffffff
#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT 0
#define REG_DPU_EW_OP_VALUE_4 0x000040a0
#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK 0xffffffff
#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT 0
#define REG_DPU_EW_OP_VALUE_5 0x000040a4
#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK 0xffffffff
#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT 0
#define REG_DPU_EW_OP_VALUE_6 0x000040a8
#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK 0xffffffff
#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT 0
#define REG_DPU_EW_OP_VALUE_7 0x000040ac
#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK 0xffffffff
#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT 0
#define REG_DPU_SURFACE_ADD 0x000040c0
#define DPU_SURFACE_ADD_SURF_ADD__MASK 0xfffffff0
#define DPU_SURFACE_ADD_SURF_ADD__SHIFT 4
#define DPU_SURFACE_ADD_RESERVED_0__MASK 0x0000000f
#define DPU_SURFACE_ADD_RESERVED_0__SHIFT 0
#define REG_DPU_LUT_ACCESS_CFG 0x00004100
#define DPU_LUT_ACCESS_CFG_RESERVED_0__MASK 0xfffc0000
#define DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT 18
#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK 0x00020000
#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT 17
#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK 0x00010000
#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT 16
#define DPU_LUT_ACCESS_CFG_RESERVED_1__MASK 0x0000fc00
#define DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT 10
#define DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK 0x000003ff
#define DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT 0
#define REG_DPU_LUT_ACCESS_DATA 0x00004104
#define DPU_LUT_ACCESS_DATA_RESERVED_0__MASK 0xffff0000
#define DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT 16
#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK 0x0000ffff
#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT 0
#define REG_DPU_LUT_CFG 0x00004108
#define DPU_LUT_CFG_RESERVED_0__MASK 0xffffff00
#define DPU_LUT_CFG_RESERVED_0__SHIFT 8
#define DPU_LUT_CFG_LUT_CAL_SEL__MASK 0x00000080
#define DPU_LUT_CFG_LUT_CAL_SEL__SHIFT 7
#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK 0x00000040
#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT 6
#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK 0x00000020
#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT 5
#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK 0x00000010
#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT 4
#define DPU_LUT_CFG_LUT_LO_LE_MUX__MASK 0x0000000c
#define DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT 2
#define DPU_LUT_CFG_LUT_EXPAND_EN__MASK 0x00000002
#define DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT 1
#define DPU_LUT_CFG_LUT_ROAD_SEL__MASK 0x00000001
#define DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT 0
#define REG_DPU_LUT_INFO 0x0000410c
#define DPU_LUT_INFO_RESERVED_0__MASK 0xff000000
#define DPU_LUT_INFO_RESERVED_0__SHIFT 24
#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK 0x00ff0000
#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT 16
#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK 0x0000ff00
#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT 8
#define DPU_LUT_INFO_RESERVED_1__MASK 0x000000ff
#define DPU_LUT_INFO_RESERVED_1__SHIFT 0
#define REG_DPU_LUT_LE_START 0x00004110
#define DPU_LUT_LE_START_LUT_LE_START__MASK 0xffffffff
#define DPU_LUT_LE_START_LUT_LE_START__SHIFT 0
#define REG_DPU_LUT_LE_END 0x00004114
#define DPU_LUT_LE_END_LUT_LE_END__MASK 0xffffffff
#define DPU_LUT_LE_END_LUT_LE_END__SHIFT 0
#define REG_DPU_LUT_LO_START 0x00004118
#define DPU_LUT_LO_START_LUT_LO_START__MASK 0xffffffff
#define DPU_LUT_LO_START_LUT_LO_START__SHIFT 0
#define REG_DPU_LUT_LO_END 0x0000411c
#define DPU_LUT_LO_END_LUT_LO_END__MASK 0xffffffff
#define DPU_LUT_LO_END_LUT_LO_END__SHIFT 0
#define REG_DPU_LUT_LE_SLOPE_SCALE 0x00004120
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK 0xffff0000
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT 16
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK 0x0000ffff
#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT 0
#define REG_DPU_LUT_LE_SLOPE_SHIFT 0x00004124
#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK 0xfffffc00
#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT 10
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK 0x000003e0
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT 5
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK 0x0000001f
#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT 0
#define REG_DPU_LUT_LO_SLOPE_SCALE 0x00004128
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK 0xffff0000
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT 16
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK 0x0000ffff
#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT 0
#define REG_DPU_LUT_LO_SLOPE_SHIFT 0x0000412c
#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK 0xfffffc00
#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT 10
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK 0x000003e0
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT 5
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK 0x0000001f
#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT 0
#define REG_DPU_RDMA_RDMA_S_STATUS 0x00005000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK 0xfffc0000
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT 18
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK 0x00030000
#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT 16
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK 0x0000fffc
#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT 2
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK 0x00000003
#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_S_POINTER 0x00005004
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK 0xfffe0000
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT 17
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK 0x00010000
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT 16
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT 6
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT 3
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT 1
#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK 0x00000001
#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT 0
#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE 0x00005008
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH 0x0000500c
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT 0x00005010
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xe0000000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 29
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK 0x1fff0000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT 16
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x0000e000
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL 0x00005014
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xffffe000
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 13
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR 0x00005018
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_BRDMA_CFG 0x0000501c
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK 0xffffffe0
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT 5
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK 0x0000001e
#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT 1
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK 0x00000001
#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT 0
#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR 0x00005020
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_NRDMA_CFG 0x00005028
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK 0xffffffe0
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT 5
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK 0x0000001e
#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT 1
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK 0x00000001
#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT 0
#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR 0x0000502c
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_ERDMA_CFG 0x00005034
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK 0xc0000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT 30
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK 0x20000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT 29
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK 0x10000000
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT 28
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK 0x0ffffff0
#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT 4
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK 0x0000000c
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT 2
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK 0x00000002
#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT 1
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK 0x00000001
#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR 0x00005038
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK 0xffffffff
#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE 0x00005040
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK 0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT 4
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG 0x00005044
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK 0xfffc0000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT 18
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK 0x00038000
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT 15
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK 0x00007800
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT 11
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK 0x00000700
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT 8
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK 0x000000e0
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT 5
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK 0x00000010
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT 4
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK 0x00000008
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT 3
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000006
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT 1
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG 0x00005048
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK 0xfff80000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT 19
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK 0x0007c000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT 14
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK 0x00002000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT 13
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK 0x00001000
#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT 12
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK 0x00000e00
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT 9
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK 0x000001c0
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT 6
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK 0x00000038
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT 3
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK 0x00000007
#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT 0
#define REG_DPU_RDMA_RDMA_SURF_NOTCH 0x0000504c
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK 0xfffffff0
#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT 4
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT 0
#define REG_DPU_RDMA_RDMA_PAD_CFG 0x00005064
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK 0xffff0000
#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT 16
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK 0x0000ff80
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT 7
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK 0x00000070
#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT 4
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK 0x00000008
#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT 3
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK 0x00000007
#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT 0
#define REG_DPU_RDMA_RDMA_WEIGHT 0x00005068
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK 0xff000000
#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT 24
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK 0x00ff0000
#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT 16
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK 0x0000ff00
#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT 8
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK 0x000000ff
#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT 0
#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH 0x0000506c
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK 0xfffffff0
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT 4
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT 0
#endif
userspace/npu-probe/coredpu_reference.txt
+1044
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File diff suppressed because it is too large Load Diff
userspace/npu-probe/librocket.c
+96
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@@ -0,0 +1,96 @@
/* SPDX-License-Identifier: MIT */
/*
* librocket — thin C wrapper over the Rockchip "rocket" NPU DRM-accel uAPI.
*
* Implementation — pure syscall-surface plumbing.
*/
#include "librocket.h"
#include <errno.h>
#include <fcntl.h>
#include <string.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include <unistd.h>
int rocket_open(const char *path)
{
int fd = open(path, O_RDWR | O_CLOEXEC);
if (fd < 0)
return -errno;
return fd;
}
int rocket_create_bo(int fd, uint32_t size, uint32_t *handle_out,
uint64_t *dma_address_out, uint64_t *mmap_offset_out)
{
struct drm_rocket_create_bo create_bo;
int ret;
memset(&create_bo, 0, sizeof(create_bo));
create_bo.size = size;
ret = ioctl(fd, DRM_IOCTL_ROCKET_CREATE_BO, &create_bo);
if (ret < 0)
return -errno;
if (handle_out)
*handle_out = create_bo.handle;
if (dma_address_out)
*dma_address_out = create_bo.dma_address;
if (mmap_offset_out)
*mmap_offset_out = create_bo.offset;
return 0;
}
void *rocket_mmap_bo(int fd, uint64_t mmap_offset, uint32_t size)
{
return mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd,
mmap_offset);
}
int rocket_prep_bo(int fd, uint32_t handle, int64_t timeout_ns)
{
struct drm_rocket_prep_bo prep_bo;
int ret;
memset(&prep_bo, 0, sizeof(prep_bo));
prep_bo.handle = handle;
prep_bo.timeout_ns = timeout_ns;
ret = ioctl(fd, DRM_IOCTL_ROCKET_PREP_BO, &prep_bo);
if (ret < 0)
return -errno;
return 0;
}
int rocket_fini_bo(int fd, uint32_t handle)
{
struct drm_rocket_fini_bo fini_bo;
int ret;
memset(&fini_bo, 0, sizeof(fini_bo));
fini_bo.handle = handle;
ret = ioctl(fd, DRM_IOCTL_ROCKET_FINI_BO, &fini_bo);
if (ret < 0)
return -errno;
return 0;
}
int rocket_submit(int fd, struct drm_rocket_job *jobs, uint32_t job_count)
{
struct drm_rocket_submit submit;
int ret;
memset(&submit, 0, sizeof(submit));
submit.jobs = (uintptr_t)jobs;
submit.job_count = job_count;
submit.job_struct_size = sizeof(struct drm_rocket_job);
ret = ioctl(fd, DRM_IOCTL_ROCKET_SUBMIT, &submit);
if (ret < 0)
return -errno;
return 0;
}
userspace/npu-probe/librocket.h
+84
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@@ -0,0 +1,84 @@
/* SPDX-License-Identifier: MIT */
/*
* librocket — thin C wrapper over the Rockchip "rocket" NPU DRM-accel uAPI.
*
* This is pure syscall-surface plumbing. No NPU/tensor semantics, no register
* commands. Every function returns 0 on success or -errno on failure (except
* rocket_mmap_bo which returns the mmap'd pointer or MAP_FAILED).
*/
#ifndef LIBROCKET_H
#define LIBROCKET_H
#include "rocket_accel.h"
#include <stdint.h>
#include <sys/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* rocket_open - open a rocket NPU accel device
* @path: device node path (e.g. "/dev/accel/accel0")
*
* Returns the file descriptor on success, or -errno on failure.
*/
int rocket_open(const char *path);
/**
* rocket_create_bo - allocate a buffer object
* @fd: rocket device fd
* @size: desired BO size in bytes
* @handle_out: on success, written with the GEM handle
* @dma_address_out: on success, written with the NPU DMA address
* @mmap_offset_out: on success, written with the mmap offset
*
* Returns 0 on success, -errno on failure.
*/
int rocket_create_bo(int fd, uint32_t size, uint32_t *handle_out,
uint64_t *dma_address_out, uint64_t *mmap_offset_out);
/**
* rocket_mmap_bo - mmap a BO into userspace
* @fd: rocket device fd
* @mmap_offset: offset returned by rocket_create_bo
* @size: number of bytes to map
*
* Returns the mapped pointer, or MAP_FAILED on failure.
*/
void *rocket_mmap_bo(int fd, uint64_t mmap_offset, uint32_t size);
/**
* rocket_prep_bo - take CPU ownership of a BO (wait for NPU, sync caches)
* @fd: rocket device fd
* @handle: GEM handle of the BO
* @timeout_ns: max wait time in nanoseconds (-1 for infinite)
*
* Returns 0 on success, -errno on failure.
*/
int rocket_prep_bo(int fd, uint32_t handle, int64_t timeout_ns);
/**
* rocket_fini_bo - hand a BO back to the device (sync caches)
* @fd: rocket device fd
* @handle: GEM handle of the BO
*
* Returns 0 on success, -errno on failure.
*/
int rocket_fini_bo(int fd, uint32_t handle);
/**
* rocket_submit - submit NPU jobs
* @fd: rocket device fd
* @jobs: pointer to an array of struct drm_rocket_job
* @job_count: number of jobs in the array
*
* Returns 0 on success, -errno on failure.
*/
int rocket_submit(int fd, struct drm_rocket_job *jobs, uint32_t job_count);
#ifdef __cplusplus
}
#endif
#endif /* LIBROCKET_H */
userspace/npu-probe/rkt_matmul.h
+55
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/*
* rkt_matmul.h — Rockchip "rocket" NPU matmul regcmd generator
*
* Builds a register-command stream for a single INT8 matmul
* Y[M][N] = X[M][K] * W[K][N] expressed as a 1×1 convolution.
*
* Faithfully adapted from the upstream Mesa "rocket" Gallium driver
* (rkt_regcmd.c, rkt_task.c, rkt_ml.c, rkt_registers.h).
*
* SPDX-License-Identifier: MIT
*/
#ifndef RKT_MATMUL_H
#define RKT_MATMUL_H
#include <stdint.h>
/**
* rkt_build_matmul_regcmd - build a single-task NPU regcmd for an INT8 matmul
*
* The matmul is emitted as a 1×1 convolution on the NPU:
* input_channels = K
* kernels = N
* height = M (conv spatial rows)
* width = 1 (conv spatial columns)
*
* @param out caller-provided output buffer
* @param out_capacity max uint64_t entries in @out
* @param M number of rows of X (and rows of Y)
* @param N number of columns of W (and columns of Y)
* @param K number of columns of X / rows of W
* @param input_dma bus address of X[M][K] (must be 256-byte aligned)
* @param weights_dma bus address of W[K][N] (must be 256-byte aligned)
* @param output_dma bus address of Y[M][N] (must be 256-byte aligned)
* @param input_zero_point int8 zero-point for input (0-255, usually 128)
* @param weight_zero_point int8 zero-point for weights (0-255, usually 128)
* @param output_zero_point int8 zero-point for output (0-255, usually 128)
*
* @return number of uint64_t commands written, or -1 if capacity exceeded.
*
* NOTE: Rate/scale parameters are not exposed. This generator assumes
* input_scale = weights_scale = output_scale = 1.0 (identity requantisation).
* Callers requiring proper quantised output must patch REG_DPU_OUT_CVT_SCALE
* and REG_DPU_OUT_CVT_SHIFT after construction, or provide pre-computed
* scale/shift values via an extended API.
*/
int rkt_build_matmul_regcmd(uint64_t *out, int out_capacity,
uint32_t M, uint32_t N, uint32_t K,
uint64_t input_dma, uint64_t weights_dma,
uint64_t output_dma,
int32_t input_zero_point,
int32_t weight_zero_point,
int32_t output_zero_point);
#endif /* RKT_MATMUL_H */
userspace/npu-probe/rkt_matmul_cna.c
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#include "rkt_matmul_cna.h"
#include "cna_defs.h"
#include <stdint.h>
/*
* Packed register command: (target << 48) | (value << 16) | reg
* target = block_enum + 1. CNA block = 0x200 -> target 0x201; DPU = 0x1000 -> 0x1001.
*/
static int rkt_push(uint64_t *out, int *n, int cap, uint32_t target,
uint32_t reg, uint32_t value)
{
if (*n >= cap)
return -1;
out[*n] = ((uint64_t)target << 48) | ((uint64_t)value << 16) | (uint64_t)reg;
(*n)++;
return 0;
}
#define EMIT_CNA(reg, val) do { if (rkt_push(out, &n, cap, 0x201, (reg), (val)) < 0) return -1; } while (0)
#define EMIT_DPU(reg, val) do { if (rkt_push(out, &n, cap, 0x1001, (reg), (val)) < 0) return -1; } while (0)
/* Field-set: (value << FIELD__SHIFT) & FIELD__MASK */
#define F(v, name) (((uint32_t)(v) << name##__SHIFT) & name##__MASK)
int rkt_emit_cna(uint64_t *out, int cap, const struct cna_params *p)
{
int n = 0;
/* ==== CNA emit sequence (Montessori, chunk by chunk) ==== */
uint32_t con0 = F(p->weights_banks, CNA_CBUF_CON0_WEIGHT_BANK) |
F(p->input_banks, CNA_CBUF_CON0_DATA_BANK);
if (p->task_num > 0 && p->reuse_weights_cbuf)
con0 |= F(1, CNA_CBUF_CON0_WEIGHT_REUSE);
EMIT_CNA(REG_CNA_CBUF_CON0, con0);
EMIT_CNA(REG_CNA_DCOMP_REGNUM, 0);
EMIT_CNA(REG_CNA_DCOMP_CTRL, 0);
uint32_t con1 = 0x0;
if (p->input_channels_real == 1) {
con1 |= F(1, CNA_CONV_CON1_NONALIGN_DMA) | F(1, CNA_CONV_CON1_GROUP_LINE_OFF) |
F(8, CNA_CONV_CON1_ARGB_IN);
}
if (p->depthwise)
con1 |= F(3, CNA_CONV_CON1_CONV_MODE);
EMIT_CNA(REG_CNA_CONV_CON1, con1);
EMIT_DPU(REG_DPU_S_POINTER, F(1, DPU_S_POINTER_POINTER_PP_MODE) |
F(1, DPU_S_POINTER_EXECUTER_PP_EN) |
F(1, DPU_S_POINTER_POINTER_PP_EN));
EMIT_DPU(REG_DPU_RDMA_RDMA_S_POINTER,
F(1, DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE) |
F(1, DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN) |
F(1, DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN));
EMIT_CNA(REG_CNA_CONV_CON1, con1);
EMIT_CNA(REG_CNA_CONV_CON2,
F(50 + p->stride_y + 1, CNA_CONV_CON2_FEATURE_GRAINS)); /* Magic: Seems to pass the most tests */
EMIT_CNA(REG_CNA_CONV_CON3, F(p->stride_x, CNA_CONV_CON3_CONV_X_STRIDE) |
F(p->stride_y, CNA_CONV_CON3_CONV_Y_STRIDE));
EMIT_CNA(REG_CNA_DATA_SIZE0,
F(p->input_width, CNA_DATA_SIZE0_DATAIN_WIDTH) |
F(p->input_height, CNA_DATA_SIZE0_DATAIN_HEIGHT));
EMIT_CNA(REG_CNA_DATA_SIZE1,
F(p->input_channels_real - 1, CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL) |
F(p->input_channels, CNA_DATA_SIZE1_DATAIN_CHANNEL));
EMIT_CNA(REG_CNA_DATA_SIZE2, F(p->output_width, CNA_DATA_SIZE2_DATAOUT_WIDTH));
EMIT_CNA(REG_CNA_DATA_SIZE3, F(p->atomic_count, CNA_DATA_SIZE3_DATAOUT_ATOMICS));
EMIT_CNA(REG_CNA_WEIGHT_SIZE0, p->weights_width * p->weights_height *
p->input_channels * p->weights_kernels);
EMIT_CNA(REG_CNA_WEIGHT_SIZE1,
p->weights_width * p->weights_height * p->input_channels);
EMIT_CNA(REG_CNA_WEIGHT_SIZE2,
F(p->weights_width, CNA_WEIGHT_SIZE2_WEIGHT_WIDTH) |
F(p->weights_height, CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT) |
F(p->weights_kernels, CNA_WEIGHT_SIZE2_WEIGHT_KERNELS));
EMIT_CNA(REG_CNA_CBUF_CON0, con0);
EMIT_CNA(REG_CNA_CBUF_CON1, F(p->input_data_entries, CNA_CBUF_CON1_DATA_ENTRIES));
if (p->input_channels_real == 1) {
unsigned truncate = 14;
unsigned scale = 16384;
unsigned offset = 65408;
if (p->addition_input || p->add_tensor != -1) {
truncate = 15;
scale = 32388;
}
EMIT_CNA(REG_CNA_CVT_CON0, F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_3) |
F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_2) |
F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_1) |
F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_0));
EMIT_CNA(REG_CNA_CVT_CON1,
F(scale, CNA_CVT_CON1_CVT_SCALE0) | F(offset, CNA_CVT_CON1_CVT_OFFSET0));
EMIT_CNA(REG_CNA_CVT_CON2,
F(scale, CNA_CVT_CON2_CVT_SCALE1) | F(offset, CNA_CVT_CON2_CVT_OFFSET1));
EMIT_CNA(REG_CNA_CVT_CON3,
F(scale, CNA_CVT_CON3_CVT_SCALE2) | F(offset, CNA_CVT_CON3_CVT_OFFSET2));
EMIT_CNA(REG_CNA_CVT_CON4,
F(scale, CNA_CVT_CON4_CVT_SCALE3) | F(offset, CNA_CVT_CON4_CVT_OFFSET3));
} else {
EMIT_CNA(REG_CNA_CVT_CON0, F(1, CNA_CVT_CON0_DATA_SIGN) |
F(1, CNA_CVT_CON0_CVT_TYPE) |
F(1, CNA_CVT_CON0_CVT_BYPASS));
EMIT_CNA(REG_CNA_CVT_CON1, F(1, CNA_CVT_CON1_CVT_SCALE0));
EMIT_CNA(REG_CNA_CVT_CON2, F(1, CNA_CVT_CON2_CVT_SCALE1));
EMIT_CNA(REG_CNA_CVT_CON3, F(1, CNA_CVT_CON3_CVT_SCALE2));
EMIT_CNA(REG_CNA_CVT_CON4, F(1, CNA_CVT_CON4_CVT_SCALE3));
}
EMIT_CNA(REG_CNA_FC_CON0, 0);
EMIT_CNA(REG_CNA_FC_CON1, 0);
EMIT_CNA(REG_CNA_CONV_CON2,
F(50 + p->stride_y + 1, CNA_CONV_CON2_FEATURE_GRAINS)); /* Magic: Seems to pass the most tests */
EMIT_CNA(REG_CNA_CONV_CON3, F(p->stride_x, CNA_CONV_CON3_CONV_X_STRIDE) |
F(p->stride_y, CNA_CONV_CON3_CONV_Y_STRIDE));
EMIT_CNA(REG_CNA_DATA_SIZE0,
F(p->input_width, CNA_DATA_SIZE0_DATAIN_WIDTH) |
F(p->input_height, CNA_DATA_SIZE0_DATAIN_HEIGHT));
EMIT_CNA(REG_CNA_DATA_SIZE1,
F(p->input_channels_real - 1, CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL) |
F(p->input_channels, CNA_DATA_SIZE1_DATAIN_CHANNEL));
EMIT_CNA(REG_CNA_DATA_SIZE2, F(p->output_width, CNA_DATA_SIZE2_DATAOUT_WIDTH));
EMIT_CNA(REG_CNA_DATA_SIZE3, F(p->atomic_count, CNA_DATA_SIZE3_DATAOUT_ATOMICS));
EMIT_CNA(REG_CNA_WEIGHT_SIZE0, p->weights_width * p->weights_height *
p->input_channels * p->weights_kernels);
EMIT_CNA(REG_CNA_WEIGHT_SIZE1,
p->weights_width * p->weights_height * p->input_channels);
EMIT_CNA(REG_CNA_WEIGHT_SIZE2,
F(p->weights_width, CNA_WEIGHT_SIZE2_WEIGHT_WIDTH) |
F(p->weights_height, CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT) |
F(p->weights_kernels, CNA_WEIGHT_SIZE2_WEIGHT_KERNELS));
EMIT_CNA(REG_CNA_CBUF_CON0, con0);
EMIT_CNA(REG_CNA_CBUF_CON1, F(p->input_data_entries, CNA_CBUF_CON1_DATA_ENTRIES));
if (p->input_channels_real == 1) {
unsigned truncate = 14;
unsigned scale = 16384;
unsigned offset = 65408;
if (p->addition_input || p->add_tensor != -1) {
truncate = 15;
scale = 32388;
}
EMIT_CNA(REG_CNA_CVT_CON0, F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_3) |
F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_2) |
F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_1) |
F(truncate, CNA_CVT_CON0_CVT_TRUNCATE_0));
EMIT_CNA(REG_CNA_CVT_CON1,
F(scale, CNA_CVT_CON1_CVT_SCALE0) | F(offset, CNA_CVT_CON1_CVT_OFFSET0));
EMIT_CNA(REG_CNA_CVT_CON2,
F(scale, CNA_CVT_CON2_CVT_SCALE1) | F(offset, CNA_CVT_CON2_CVT_OFFSET1));
EMIT_CNA(REG_CNA_CVT_CON3,
F(scale, CNA_CVT_CON3_CVT_SCALE2) | F(offset, CNA_CVT_CON3_CVT_OFFSET2));
EMIT_CNA(REG_CNA_CVT_CON4,
F(scale, CNA_CVT_CON4_CVT_SCALE3) | F(offset, CNA_CVT_CON4_CVT_OFFSET3));
} else {
EMIT_CNA(REG_CNA_CVT_CON0, F(1, CNA_CVT_CON0_DATA_SIGN) |
F(1, CNA_CVT_CON0_CVT_TYPE) |
F(1, CNA_CVT_CON0_CVT_BYPASS));
EMIT_CNA(REG_CNA_CVT_CON1, F(1, CNA_CVT_CON1_CVT_SCALE0));
EMIT_CNA(REG_CNA_CVT_CON2, F(1, CNA_CVT_CON2_CVT_SCALE1));
EMIT_CNA(REG_CNA_CVT_CON3, F(1, CNA_CVT_CON3_CVT_SCALE2));
EMIT_CNA(REG_CNA_CVT_CON4, F(1, CNA_CVT_CON4_CVT_SCALE3));
}
EMIT_CNA(REG_CNA_FC_CON0, 0);
EMIT_CNA(REG_CNA_FC_CON1, 0);
EMIT_CNA(REG_CNA_PAD_CON0, F(p->pad_left, CNA_PAD_CON0_PAD_LEFT) |
F(p->pad_top, CNA_PAD_CON0_PAD_TOP));
EMIT_CNA(REG_CNA_FEATURE_DATA_ADDR,
(uint32_t)p->input_dma);
EMIT_CNA(REG_CNA_FC_CON2, 0);
EMIT_CNA(REG_CNA_DMA_CON0,
F(15, CNA_DMA_CON0_WEIGHT_BURST_LEN) | F(15, CNA_DMA_CON0_DATA_BURST_LEN));
EMIT_CNA(REG_CNA_DMA_CON1, F(p->input_line_stride, CNA_DMA_CON1_LINE_STRIDE));
EMIT_CNA(REG_CNA_DMA_CON2, F(p->input_surface_stride, CNA_DMA_CON2_SURF_STRIDE));
EMIT_CNA(REG_CNA_FC_DATA_SIZE0,
F(p->input_width, CNA_FC_DATA_SIZE0_DMA_WIDTH) |
F(p->input_height, CNA_FC_DATA_SIZE0_DMA_HEIGHT));
EMIT_CNA(REG_CNA_FC_DATA_SIZE1,
F(p->input_channels, CNA_FC_DATA_SIZE1_DMA_CHANNEL));
EMIT_CNA(REG_CNA_DCOMP_CTRL, 0);
EMIT_CNA(REG_CNA_DCOMP_REGNUM, 0);
EMIT_CNA(REG_CNA_DCOMP_ADDR0, (uint32_t)p->weights_dma);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT0, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT1, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT2, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT3, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT4, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT5, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT6, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT7, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT8, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT9, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT10, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT11, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT12, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT13, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT14, 0);
EMIT_CNA(REG_CNA_DCOMP_AMOUNT15, 0);
if (p->input_channels_real == 1) {
EMIT_CNA(REG_CNA_CVT_CON5, 65535);
} else {
EMIT_CNA(REG_CNA_CVT_CON5, 0);
}
int32_t pad_con1;
if (p->weights_width >= 3 && p->input_zero_point == 0x0)
pad_con1 = 0xffff8080;
else
pad_con1 = p->input_zero_point - 0x80;
if (p->addition_input || p->add_tensor != -1)
pad_con1 = 0xffffff80;
if (p->depthwise && p->input_zero_point == 0x8b)
pad_con1 = 0x0b0b;
EMIT_CNA(REG_CNA_PAD_CON1, pad_con1);
/* ==== end CNA stage ==== */
return n;
}
userspace/npu-probe/rkt_matmul_cna.h
+25
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#ifndef RKT_MATMUL_CNA_H
#define RKT_MATMUL_CNA_H
#include <stdint.h>
/* All the task-/operation-level fields the Mesa CNA emit reads, flattened. */
struct cna_params {
uint32_t input_width, input_height, input_channels, input_channels_real;
uint32_t output_width, atomic_count;
uint32_t weights_width, weights_height, weights_kernels;
uint32_t weights_banks, input_banks, input_data_entries;
uint32_t input_line_stride, input_surface_stride;
uint64_t input_dma, weights_dma; /* NPU DMA addresses of the input/weight BOs */
uint32_t stride_x, stride_y;
uint32_t pad_left, pad_right, pad_top, pad_bottom;
int32_t output_zero_point, weights_zero_point, input_zero_point;
int depthwise, reuse_weights_cbuf, addition_input, add_tensor;
unsigned task_num; /* 0 for the first/only task */
};
/* Append the CNA-stage register commands (packed uint64_t) into out[] (capacity cap).
Returns the number of commands written, or -1 if capacity would be exceeded. */
int rkt_emit_cna(uint64_t *out, int cap, const struct cna_params *p);
#endif /* RKT_MATMUL_CNA_H */
userspace/npu-probe/rkt_matmul_coredpu.c
+33
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#include "rkt_matmul_coredpu.h"
#include "coredpu_defs.h"
#include <stdint.h>
/* Packed register command: (target<<48) | (value<<16) | reg. target = block_enum + 1.
CORE=0x800->0x801, DPU=0x1000->0x1001, PC=0x100->0x101. */
static int rkt_push(uint64_t *out, int *n, int cap, uint32_t target,
uint32_t reg, uint32_t value)
{
if (*n >= cap)
return -1;
out[*n] = ((uint64_t)target << 48) | ((uint64_t)value << 16) | (uint64_t)reg;
(*n)++;
return 0;
}
#define EMIT_CORE(reg, val) do { if (rkt_push(out, &n, cap, 0x801, (reg), (val)) < 0) return -1; } while (0)
#define EMIT_DPU(reg, val) do { if (rkt_push(out, &n, cap, 0x1001, (reg), (val)) < 0) return -1; } while (0)
#define EMIT_PC(reg, val) do { if (rkt_push(out, &n, cap, 0x101, (reg), (val)) < 0) return -1; } while (0)
#define EMIT_RAW(tgt, reg, val) do { if (rkt_push(out, &n, cap, (tgt), (reg), (val)) < 0) return -1; } while (0)
#define F(v, name) (((uint32_t)(v) << name##__SHIFT) & name##__MASK)
int rkt_emit_coredpu(uint64_t *out, int cap, const struct coredpu_params *p)
{
int n = 0;
(void)p;
/* ==== CORE + DPU + PC emit (filled by slice) ==== */
/* @@INSERT@@ */
return n;
}
userspace/npu-probe/rkt_matmul_coredpu.h
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#ifndef RKT_MATMUL_COREDPU_H
#define RKT_MATMUL_COREDPU_H
#include <stdint.h>
/* Fields the Mesa CORE/DPU/PC emit reads (task-/operation-level flattened). */
struct coredpu_params {
uint32_t input_width;
uint32_t output_width, output_height;
uint32_t output_channels, output_channels_real;
uint32_t output_offset, output_surface_stride, surfaces_per_row;
uint32_t truncate_bits;
int depthwise;
int32_t addition_offset;
int32_t add_tensor; /* index, or -1 if none */
float input_scale, weights_scale, output_scale, addition_scale;
uint64_t output_addr, add_tensor_addr, biases_addr; /* pre-computed DMA addresses */
};
/* Append CORE+DPU+PC register commands (packed uint64_t) into out[] (capacity cap).
Returns number written, or -1 on overflow. */
int rkt_emit_coredpu(uint64_t *out, int cap, const struct coredpu_params *p);
#endif /* RKT_MATMUL_COREDPU_H */
userspace/npu-probe/rocket_accel.h
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/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2024 Tomeu Vizoso
*/
#ifndef __DRM_UAPI_ROCKET_ACCEL_H__
#define __DRM_UAPI_ROCKET_ACCEL_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_ROCKET_CREATE_BO 0x00
#define DRM_ROCKET_SUBMIT 0x01
#define DRM_ROCKET_PREP_BO 0x02
#define DRM_ROCKET_FINI_BO 0x03
#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
#define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct drm_rocket_submit)
#define DRM_IOCTL_ROCKET_PREP_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo)
#define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_FINI_BO, struct drm_rocket_fini_bo)
/**
* struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
*
*/
struct drm_rocket_create_bo {
/**
* @size: Input: Size of the requested BO.
*/
__u32 size;
/**
* @handle: Output: GEM handle for the BO.
*/
__u32 handle;
/**
* @dma_address: Output: DMA address for the BO in the NPU address
* space. This address is private to the DRM fd and is valid for
* the lifetime of the GEM handle.
*/
__u64 dma_address;
/**
* @offset: Output: Offset into the drm node to use for subsequent
* mmap call.
*/
__u64 offset;
};
/**
* struct drm_rocket_prep_bo - ioctl argument for starting CPU ownership of the BO.
*
* Takes care of waiting for any NPU jobs that might still use the NPU and performs cache
* synchronization.
*/
struct drm_rocket_prep_bo {
/**
* @handle: Input: GEM handle of the buffer object.
*/
__u32 handle;
/**
* @reserved: Reserved, must be zero.
*/
__u32 reserved;
/**
* @timeout_ns: Input: Amount of time to wait for NPU jobs.
*/
__s64 timeout_ns;
};
/**
* struct drm_rocket_fini_bo - ioctl argument for finishing CPU ownership of the BO.
*
* Synchronize caches for NPU access.
*/
struct drm_rocket_fini_bo {
/**
* @handle: Input: GEM handle of the buffer object.
*/
__u32 handle;
/**
* @reserved: Reserved, must be zero.
*/
__u32 reserved;
};
/**
* struct drm_rocket_task - A task to be run on the NPU
*
* A task is the smallest unit of work that can be run on the NPU.
*/
struct drm_rocket_task {
/**
* @regcmd: Input: DMA address to NPU mapping of register command buffer
*/
__u32 regcmd;
/**
* @regcmd_count: Input: Number of commands in the register command
* buffer
*/
__u32 regcmd_count;
};
/**
* struct drm_rocket_job - A job to be run on the NPU
*
* The kernel will schedule the execution of this job taking into account its
* dependencies with other jobs. All tasks in the same job will be executed
* sequentially on the same core, to benefit from memory residency in SRAM.
*/
struct drm_rocket_job {
/**
* @tasks: Input: Pointer to an array of struct drm_rocket_task.
*/
__u64 tasks;
/**
* @in_bo_handles: Input: Pointer to a u32 array of the BOs that
* are read by the job.
*/
__u64 in_bo_handles;
/**
* @out_bo_handles: Input: Pointer to a u32 array of the BOs that
* are written to by the job.
*/
__u64 out_bo_handles;
/**
* @task_count: Input: Number of tasks passed in.
*/
__u32 task_count;
/**
* @task_struct_size: Input: Size in bytes of the structs in the
* @tasks field.
*/
__u32 task_struct_size;
/**
* @in_bo_handle_count: Input: Number of input BO handles passed in
* (size is that times 4).
*/
__u32 in_bo_handle_count;
/**
* @out_bo_handle_count: Input: Number of output BO handles passed in
* (size is that times 4).
*/
__u32 out_bo_handle_count;
};
/**
* struct drm_rocket_submit - ioctl argument for submitting commands to the NPU.
*
* The kernel will schedule the execution of these jobs in dependency order.
*/
struct drm_rocket_submit {
/**
* @jobs: Input: Pointer to an array of struct drm_rocket_job.
*/
__u64 jobs;
/**
* @job_count: Input: Number of jobs passed in.
*/
__u32 job_count;
/**
* @job_struct_size: Input: Size in bytes of the structs in the
* @jobs field.
*/
__u32 job_struct_size;
/**
* @reserved: Reserved, must be zero.
*/
__u64 reserved;
};
#if defined(__cplusplus)
}
#endif
#endif /* __DRM_UAPI_ROCKET_ACCEL_H__ */