rosenblatt

marfrit/rosenblatt

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Author	SHA1	Message	Date
Markus Fritsche	1fb810d93c	Rosenblatt: FIRST CORRECT INT8 MATMUL ON THE MAINLINE ROCKET NPU The whole path works end-to-end on real silicon (boltzmann, 7.0.0-rc3 rocket, /dev/accel/accel0): our golden regcmd builder + rkt_operands tiling + librocket submission -> a 4x8x16 INT8 matmul whose per-element output (incl requant + int8 saturation) matches the CPU reference exactly (144,160,...,255). ROOT CAUSE of the long all-zero saga: rocket_prep_bo()'s timeout_ns is an ABSOLUTE CLOCK_MONOTONIC deadline (kernel drm_timeout_abs_to_jiffies), not a relative duration. hwtest passed 3e9 ('3s') -> read as a deadline ~9h in the past -> effective timeout 0 -> we read the output BO (memset 0) BEFORE the NPU wrote it. The -EBUSY we dismissed WAS the 'not done' signal. Mesa passes INT64_MAX (block until the DPU-write fence signals). Nothing was wrong with the regcmd, operands, addresses, driver, or hardware -- diagnosed via the working Mesa Teflon reference ('if tflite works it has the proper spells', per Markus; divergence found by Fable/rknpu-specialist). Fixes: hwtest prep_bo INT64_MAX; close all BO handles (kills drm_mm_takedown WARN); librocket rocket_close_bo added + prep_bo doc corrected (abs deadline). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>	2026-07-14 08:36:14 +02:00
claude-noether	60e7709d7b	Rosenblatt Phase-2: userspace regcmd builder — U3 wrapper + CNA stage (4a) - librocket.{c,h}: thin ioctl wrapper over the rocket accel uAPI (open + CREATE_BO/ SUBMIT/PREP_BO/FINI_BO + mmap). Compiles with -I/usr/include/drm. - rkt_matmul_cna.{c,h} + cna_defs.h: CNA-stage regcmd emit for an INT8 matmul-as- 1x1-conv, faithful port of Mesa rocket fill_first_regcmd's CNA section. Compiles clean (-Wall -Wextra), 85 emits. Cross-validated: two independent ports (dspark Montessori-scaffolded + big-pickle autonomous) agree at the emit level. - rkt_matmul_coredpu.{c,h} + coredpu_defs.h: CORE+DPU+PC scaffold (empty body, @@INSERT@@ marker). Params struct incl. float scales + 3 DMA-addr fields. Body port is WIP: 82 DPU emits + float requant + PC tail remain (needs slicing). - *_reference.txt: curated Mesa rocket emit excerpts + register defines (implementer reference bundles). Implementer: dspark (DeepSeek-V4-Flash NVFP4, local) via Montessori scaffolding; autonomous CNA also produced by opencode/big-pickle. Multi-model benchmark in claude-memory reference_dspark_implementer. NOT golden-verified (faithful-to-Mesa; needs a Mesa build or NPU hardware to byte-check). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01EWpfhDgYNA21tETDP9ueBE	2026-07-13 19:23:34 +00:00

Author

SHA1

Message

Date

Markus Fritsche

1fb810d93c

Rosenblatt: FIRST CORRECT INT8 MATMUL ON THE MAINLINE ROCKET NPU

The whole path works end-to-end on real silicon (boltzmann, 7.0.0-rc3 rocket,
/dev/accel/accel0): our golden regcmd builder + rkt_operands tiling + librocket
submission -> a 4x8x16 INT8 matmul whose per-element output (incl requant +
int8 saturation) matches the CPU reference exactly (144,160,...,255).

ROOT CAUSE of the long all-zero saga: rocket_prep_bo()'s timeout_ns is an
ABSOLUTE CLOCK_MONOTONIC deadline (kernel drm_timeout_abs_to_jiffies), not a
relative duration. hwtest passed 3e9 ('3s') -> read as a deadline ~9h in the
past -> effective timeout 0 -> we read the output BO (memset 0) BEFORE the NPU
wrote it. The -EBUSY we dismissed WAS the 'not done' signal. Mesa passes
INT64_MAX (block until the DPU-write fence signals). Nothing was wrong with the
regcmd, operands, addresses, driver, or hardware -- diagnosed via the working
Mesa Teflon reference ('if tflite works it has the proper spells', per Markus;
divergence found by Fable/rknpu-specialist).

Fixes: hwtest prep_bo INT64_MAX; close all BO handles (kills drm_mm_takedown
WARN); librocket rocket_close_bo added + prep_bo doc corrected (abs deadline).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

2026-07-14 08:36:14 +02:00

claude-noether

60e7709d7b

Rosenblatt Phase-2: userspace regcmd builder — U3 wrapper + CNA stage (4a)

- librocket.{c,h}: thin ioctl wrapper over the rocket accel uAPI (open + CREATE_BO/
  SUBMIT/PREP_BO/FINI_BO + mmap). Compiles with -I/usr/include/drm.
- rkt_matmul_cna.{c,h} + cna_defs.h: CNA-stage regcmd emit for an INT8 matmul-as-
  1x1-conv, faithful port of Mesa rocket fill_first_regcmd's CNA section. Compiles
  clean (-Wall -Wextra), 85 emits. Cross-validated: two independent ports (dspark
  Montessori-scaffolded + big-pickle autonomous) agree at the emit level.
- rkt_matmul_coredpu.{c,h} + coredpu_defs.h: CORE+DPU+PC scaffold (empty body,
  @@INSERT@@ marker). Params struct incl. float scales + 3 DMA-addr fields.
  Body port is WIP: 82 DPU emits + float requant + PC tail remain (needs slicing).
- *_reference.txt: curated Mesa rocket emit excerpts + register defines (implementer
  reference bundles).

Implementer: dspark (DeepSeek-V4-Flash NVFP4, local) via Montessori scaffolding;
autonomous CNA also produced by opencode/big-pickle. Multi-model benchmark in
claude-memory reference_dspark_implementer. NOT golden-verified (faithful-to-Mesa;
needs a Mesa build or NPU hardware to byte-check).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01EWpfhDgYNA21tETDP9ueBE

2026-07-13 19:23:34 +00:00

2 Commits