marfrit
c77be48151
Replace the local host name "boltzmann" with the machine type (Rock 5 ITX+, RK3588, 32 GB) throughout so the replication docs read for anyone on the same hardware, not just this fleet. Rename fleet/boltzmann.yaml -> fleet/rock5-itx-plus.yaml.
121 lines
5.4 KiB
Markdown
121 lines
5.4 KiB
Markdown
# TODO — Rosenblatt
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Rolling punch-list. Older items at bottom (move done → DONE.md when noisy).
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---
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## Phase 1 — substrate audit
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- [ ] On the Rock 5 ITX+: `uname -r` → record in `fleet/rock5-itx-plus.yaml:kernel.running_version`
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- [ ] `find / -path '*accel*' -name '*.ko' 2>/dev/null` — check if accel framework is built
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- [ ] `ls /dev/accel/ /dev/dri/` — what's exposed?
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- [ ] `lsmod | grep -iE 'rknpu|accel'` — what's loaded?
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- [ ] `dmesg | grep -iE 'rknpu|npu|accel'` since boot — driver bringup log
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- [ ] Tomeu's rknpu series — find on lore.kernel.org/dri-devel, capture latest
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patch-set version + state (merged / in-review / dropped) → fill table in
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`docs/npu-mainline-status.md`
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- [ ] Check `drivers/accel/` in current torvalds tree — list in-tree
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accelerators, confirm rknpu's mainline state
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- [ ] Check DT bindings: `Documentation/devicetree/bindings/npu/rockchip,*.yaml`
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- [ ] Inspect `arch/arm64/boot/dts/rockchip/rk3588.dtsi` for `npu` node
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- [ ] If a userspace shim exists (rkneural?), capture repo URL + try
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hello-world against the running kernel
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- [ ] Spec-extract from BSP vendor `rockchip-npu` source — register map,
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DMA descriptor format, irq handling. No code lift; spec only.
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Phase exit criteria: `docs/npu-mainline-status.md` table fully populated;
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clear answer to "do we drive via accel uAPI or write our own MMIO driver."
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---
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## Phase 2 — formulate
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- [ ] List llama.cpp ops by wallclock %, profiling qwen-1.5B Q4_K_M on CPU
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(use llama.cpp's built-in perf-timer or perf record)
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- [ ] Pick the exact INT8 matmul tile size the NPU prefers (read from BSP source)
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- [ ] Spec out the smallest backend interface: which ops we MUST handle,
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which the framework falls back to CPU
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- [ ] Write `docs/op-coverage.md`
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---
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## Phase 3 — analyze
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- [ ] RKNPU2 SDK: trace through `librknnrt.so` user-API → kernel ioctl shapes
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(objdump + strings, no actual reverse-engineering of vendor blob — just
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the syscall surface)
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- [ ] Tomeu's accel uAPI: read driver source, understand:
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- submit-job ioctl shape
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- dmabuf import path
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- fence-wait mechanism
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- error reporting
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- [ ] BSP vendor `rockchip-npu` source: register layout, DMA descriptor
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struct, irq handling sequence
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---
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## Phase 4 — baseline
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- [ ] Build vanilla llama.cpp on the Rock 5 ITX+ (mainline branch)
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- [ ] Pull qwen2.5-1.5b-instruct Q4_K_M GGUF
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- [ ] `llama-bench -m qwen2.5-1.5b -p 512 -n 128` × 3 runs
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- [ ] Capture JSON to `benchmarks/$(date +%F)_rock5-itx-plus_qwen1.5b_cpu_baseline.json`
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- [ ] Record into `fleet/rock5-itx-plus.yaml:baseline_measurement`
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---
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## Phase-2 unblock — prerequisites (NEW, Phase-1 outflow)
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Phase-1 audit (2026-05-19) reframed Phase-2 from "design rknpu backend
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interface" to a concrete bringup sequence. See
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`docs/npu-mainline-status.md` for full context.
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- [ ] Patch the Rock 5 ITX+ board DTS / overlay to flip
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`npu@fdab0000`, `npu@fdac0000`, `npu@fdad0000` from
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`status = "disabled"` → `"okay"`. Rebuild DTB.
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- [ ] **Mitigate IOMMU v1.0 hazard before first NPU job** (32 GB host).
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Pick one:
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- (A) Boot with `mem=4G` for first-bringup validation, OR
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- (B) Carry local patches: Simon Xue per-device-ops
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(`<https://lore.kernel.org/all/20260310105303.128859-1-xxm@rock-chips.com/>`)
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+ Midgy `rockchip,rk3568-iommu-v1` discriminator compat
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+ DT update for `rknpu_mmu` to the new compat.
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- [ ] `modprobe rocket` and confirm `/dev/accel/accel0..2` appear, no
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probe errors in dmesg, IOMMU faults absent.
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- [ ] Read `drivers/accel/rocket/rocket_job.c` + Mesa Rocket Gallium to
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determine submit-job uAPI capabilities — specifically whether
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we can express a transformer matmul as a tile/op the NPU pipeline
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accepts, or whether we need additional op coverage upstream.
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- [ ] Decide matmul strategy (Phase-2 deliverable):
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conv-1×1 shoehorn / extend rocket op set / thinner submit shim.
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## Standing items — track upstream
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- [ ] Watch `drivers/iommu/rockchip-iommu.c` for the discriminator
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`rockchip,rk3568-iommu-v1` compat to land; drop local patch (B)
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when it does.
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- [ ] Watch `linux-rockchip` for the next iteration of Midgy / Simon's
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thread (last visible activity 2026-04-03).
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- [ ] Watch `drivers/accel/rocket/` for matmul / GEMM op additions.
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## Cross-phase / standing items (older)
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- [ ] Mirror Tomeu's branch — superseded: code is now in-tree.
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Keep `git.kernel.org/.../torvalds/linux.git` checkout pinned to
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the the Rock 5 ITX+ kernel rev for in-tree reading.
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- [ ] Set up serial console on the Rock 5 ITX+ for kernel-panic recovery
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(Quark umbrella; check current state) — **becomes load-bearing
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once we start poking IOMMU code.**
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- [x] Add `project_rosenblatt_overview.md` + `project_rocket_upstream_state.md`
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to claude-memory — done 2026-05-19.
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- [ ] Decide repo home: marfrit/rosenblatt on git.reauktion.de
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(probably yes, after Phase-1 substrate is captured).
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- [ ] **Resolve board-name discrepancy.** README and
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`fleet/rock5-itx-plus.yaml` say the manifest records the board type /
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`rock-5-itx-plus`; the running DT reports
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`model = "Radxa ROCK 5 ITX"`, `compatible = "radxa,rock-5-itx"`.
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Confirm physical board model (Radxa sells both SKUs) and
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either correct the README + manifest, or note that we boot
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the plain-ITX DT on ITX+ hardware (likely fine; ITX+ is mostly
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a connectivity-refresh, same SoC + same NPU silicon).
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