marfrit
c77be48151
Replace the local host name "boltzmann" with the machine type (Rock 5 ITX+, RK3588, 32 GB) throughout so the replication docs read for anyone on the same hardware, not just this fleet. Rename fleet/boltzmann.yaml -> fleet/rock5-itx-plus.yaml.
112 lines
4.9 KiB
Markdown
112 lines
4.9 KiB
Markdown
# phases — Rosenblatt per-phase log
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One entry per phase as it closes. Stores the *findings* (what we
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learned that future-us shouldn't have to rediscover) and the *next
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gate* (what Phase N+1 needs from us). Lives alongside the
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campaign-level README; this file is the durable journal.
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---
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## Phase 0 — bootstrap
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**Closed:** 2026-05-19
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**Deliverable:** repo scaffold (README, TODO, docs/, kernel/, userspace/,
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fleet/, benchmarks/), one initial commit `Rosenblatt: project scaffold
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for RK3588 NPU on mainline`.
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---
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## Phase 1 — substrate audit
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**Closed:** 2026-05-19
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**Deliverable:** `docs/npu-mainline-status.md` table fully populated;
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`fleet/rock5-itx-plus.yaml` kernel/NPU-driver block filled with live data;
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clear answer to the "accel uAPI vs. own MMIO driver" question.
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### Findings
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1. **`rocket` driver is in mainline** — Tomeu Vizoso's NPU work merged
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to torvalds in Linux 6.18 (Nov 2025) as `drivers/accel/rocket/`,
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Kconfig `DRM_ACCEL_ROCKET`. Driver author + history kept the same
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shape, but the **upstream name is `rocket`, not `rknpu`** —
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searching for `rknpu` in mainline misses everything.
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2. **The Rock 5 ITX+ already ships the driver** — `linux-rk3588-marfrit-A1`
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(7.0.0-rc3-ARCH+) is post-6.18 and contains `rocket.ko` at
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`/lib/modules/.../drivers/accel/rocket/rocket.ko`, marked
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`intree: Y`. Module aliases to `rockchip,rk3588-rknn-core`,
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matching the DT compatibles on the box.
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3. **DT nodes present but disabled** — `rk3588-base.dtsi` defines
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`rknn_core_0/1/2` at `0xfdab/c/d_0000` with compat
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`rockchip,rk3588-rknn-core`; all three boot with `status =
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"disabled"`. No board file enables them. Per-core IOMMUs
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`rknn_mmu_0/1/2` at `0xfdab9/aca/ada_000` also disabled.
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4. **Userspace is Mesa Rocket Gallium + Teflon** — shipped in Mesa
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25.3. `src/gallium/drivers/rocket/` in mesa3d main is the
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authoritative reference for regcmd construction. `rkt_regcmd.c`
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is ~700 lines, single-conv emit path. No matmul-specific code.
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5. **Kernel is a thin shim** — `drivers/accel/rocket/rocket_drv.c`
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exposes a single facade `/dev/accel/accel0` for all probed RKNN
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cores. uAPI is 4 ioctls (CREATE_BO, SUBMIT, PREP_BO, FINI_BO).
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`rocket_job_hw_submit()` powers the NPU, points
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`PC_BASE_ADDRESS` at the regcmd, sets `PC_REGISTER_AMOUNTS`,
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pulls `PC_OPERATION_ENABLE.OP_EN = 1`. Everything else is the
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userspace-built regcmd buffer.
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6. **NPU sub-blocks** identified from `rocket_registers.h` interrupt
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masks: **PC** (program controller), **CNA** (conv neural-net
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accel; FEATURE / WEIGHT / CSC channels), **CORE** (MAC array),
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**DPU** (data processing unit, requant), **PPU**
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(post-processing — not exercised by Mesa today). Each per-core
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block has 2 parallel channels for double-buffering.
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7. **Matmul-as-conv-1×1 is the only viable path** — confirmed by
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reading Mesa's emit path. INT8 matmul `Y[M,N] = X[M,K] @ W[K,N]`
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maps cleanly to a conv with width=height=1 kernel,
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`DATAIN_CHANNEL=K`, `WEIGHT_KERNELS=N`. The vendor RKNPU2 stack
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does the same shoehorn.
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8. **IOMMU v1.0 hazard surfaced from `linux-rockchip` thread**
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(Midgy BALON / Simon Xue, 2026-04-03). The NPU IOMMU is v1.0 IP
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bound to generic `rockchip,rk3568-iommu` — driven via the v2.0
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code path. v1.0 can't allocate its DTE above 4 GB. The Rock 5 ITX+
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has 32 GB. Naive enable will silently fault. Discriminator-compat
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patch series planned but **not landed in mainline master as of
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2026-05-19** (verified via cgit on
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`drivers/iommu/rockchip-iommu.c`).
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9. **Vendor stack is off-limits** — `librknnrt.so` is a closed
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binary blob under restrictive Rockchip license. BSP
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`rockchip-linux/kernel` `drivers/rknpu/` source is permitted as
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a spec-extraction reference only.
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### Phase exit decision
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**Drive via the `rocket` DRM-accel uAPI.** Writing our own MMIO
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driver would mean re-implementing IOMMU integration, power-domain
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sequencing, and fence/sched plumbing that's already in-tree and
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production-validated by Mesa Teflon consumers. The Phase-2 unblock
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list is short: DT enable + IOMMU mitigation + `modprobe rocket`.
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### Phase outflow → TODO
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Captured in `TODO.md` "Phase-2 unblock" section. Highlights:
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- Apply `kernel/dt-overlays/rk3588-rosenblatt-npu-enable.dtso` (or
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equivalent board-DTS patch) to the Rock 5 ITX+.
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- Mitigate IOMMU v1.0 hazard before first NPU job: `mem=4G` boot or
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local discriminator-compat carry.
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- `modprobe rocket`, confirm `/dev/accel/accel0`, no IOMMU faults.
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- Read `rkt_regcmd.c`, `rkt_ml.c`, `rkt_task.c`, `rkt_coefs.c` from
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Mesa for the conv-1×1 matmul encoding details (op-coverage.md
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has the first cut).
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### Memory persisted
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- `project_rosenblatt_overview.md`
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- `project_rocket_upstream_state.md` (note: name is `rocket`, not
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`rknpu`)
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- `project_iommu_v1_hazard.md`
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---
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## Phase 2 — formulate (open)
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**Status:** open as of 2026-05-19. See `TODO.md` and
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`docs/op-coverage.md` for current state of the formulation.
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