marfrit
5223d3cb3f
Phase 4 plan with 3 Phase-5 REDs applied inline: - meta layout: m.z=tmp_off, m.w=dir - sec_shift clamped to >=0 (NEON uqsub semantics) - directions table as const ivec2[14], not OR-packed Phase 6 deliverable: v3d_cdef.comp (387 inst, 2 threads, no spills). 3-way M1 (QPU vs C ref vs NEON) PASS 4096/4096. M2: 0.443 Mblock/s -> R5 = 0.116 ORANGE (predicted 0.02-0.05 RED). M4 same-kernel: NEON-3+QPU 8.46 < NEON-4 alone ~10 (negative). M4 mixed (NEON-3 MC + QPU CDEF): CPU 34.17 Mblock/s MC, QPU 0.42 Mblock/s CDEF helper. CPU side higher than the Issue 003 NEON-fallback proxy suggested - cross-substrate contention is gentler than same-side NEON contention. Verdict: CDEF stays on CPU; QPU dispatch path exists for opportunistic use. Deployment recipe table updated for all 5 cycles. Phase 9 lessons: linear extrapolation across cycles is too pessimistic; CDEF is bandwidth-bound on NEON despite high per-block ns; real-substrate-cross contention < NEON-proxy contention. - src/v3d_cdef.comp: cycle 5 QPU shader - tests/bench_v3d_cdef.c: 3-way M1, M2 bench - tests/bench_concurrent_mixed.c: K_CDEF on both sides - tests/cdef_ref.c + bench_neon_cdef.c: sec_shift clamp + expanded damping range to exercise the edge case - CMakeLists.txt: v3d_cdef.spv + bench_v3d_cdef wiring - docs/k5_cdef_phase4.md updated with Phase 5 review applied - docs/k5_cdef_phase7.md: closure doc with full verdict matrix Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
197 lines
7.8 KiB
Markdown
197 lines
7.8 KiB
Markdown
---
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cycle: 5
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phase: 7
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status: closed 2026-05-18 — M1 PASS, R₅=0.116 ORANGE, M4 same-kernel NEGATIVE, M4 mixed-kernel POSITIVE
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date_opened: 2026-05-18
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date_closed: 2026-05-18
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parent: k5_cdef_phase6 (no doc — phase 6 is the shader + bench commit)
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host: hertz
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verdict: CDEF baseline = CPU; QPU dispatch path exists for opportunistic use. Better than predicted (ORANGE not RED).
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---
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# Cycle 5, Phase 7 — Verification (CDEF on V3D)
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## Phase 6 deliverable
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- `src/v3d_cdef.comp` — 256 inv/WG, 4 blocks/WG, no barrier,
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uint16 tmp via `GL_EXT_shader_16bit_storage`, uint8 dst.
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- `tests/bench_v3d_cdef.c` — 3-way M1 (QPU vs C ref vs NEON) per
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Phase 5 YELLOW-1, M2 throughput, R₅ band classifier.
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- `tests/bench_concurrent_mixed.c` extended with K_CDEF on both
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CPU and QPU sides for M4.
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shaderdb:
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```
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SHADER-DB-4a79c02a... 387 inst, 2 threads, 0 loops, 133 uniforms,
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21 max-temps, 0:0 spills:fills, 0 sfu-stalls, 5 nops
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```
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2 threads (not 4 as plan hoped) — register pressure same as
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cycle 3 MC. 133 uniforms under the 144 gate. No spills.
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## M1 — 3-way bit-exact
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```
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=== M1₅: QPU vs C-ref vs NEON 3-way ===
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C ref vs NEON parity check: 0/4096 mismatches
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QPU vs C ref: 4096 / 4096 blocks bit-exact (100.0000%)
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QPU vs NEON: 4096 / 4096 blocks bit-exact (100.0000%)
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```
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All three implementations agree. Phase 5 RED-1, RED-2, RED-3 fixes
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verified (meta layout, sec_shift clamp, ivec2 dirs table).
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## M2 — QPU throughput
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```
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=== M2₅: QPU throughput ===
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blocks/dispatch: 4096
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iters: 50
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total blocks: 204 800
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elapsed (kernel)=0.462 s
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M2₅ throughput = 0.443 Mblock/s
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per-block = 2256.1 ns
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per-dispatch = 9241.0 us
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```
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R₅ = 0.443 / 3.809 = **0.116 → ORANGE band**.
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**Better than predicted** (Phase 4 estimated R₅ = 0.02-0.05, deep
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RED). The prediction was extrapolated from cycle 3 MC's R₃ = 0.067
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× scaling for higher per-block compute weight. The actual QPU
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overhead per block (387 inst at 2 threads) doesn't scale as
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badly as that linear projection suggested — likely because
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the constrain() inner loop has less filter-coefficient overhead
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than MC's 8-tap subpel and the 16-bit tmp loads are well-suited
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to the V3D 7.1 storage path.
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30fps@1080p floor: 0.443 / 0.972 = **0.46× margin (isolation)**.
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**Below the user-facing floor as sole substrate.** But CDEF is
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not commonly applied to every block in real video — it's
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strength-gated per superblock. Effective CDEF rate in real
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content is often < 0.5 Mblock/s. Within reach.
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## M4 — concurrent matrix
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All windows 6 s, hertz, `bench_concurrent_mixed`.
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### M4 same-kernel (cycle 5 closure)
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| Config | CPU CDEF agg | QPU CDEF | total | per-core CPU |
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|---|---|---|---|---|
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| **NEON-3 + QPU** | 8.080 | 0.381 | 8.461 | 2.69 avg |
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| **NEON-4 + QPU** | 7.866 | 0.385 | 8.251 | 1.97 avg |
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NEON-3 + QPU > NEON-4 + QPU (8.46 > 8.25). NEON CDEF is
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**bandwidth-saturated at 4 cores** despite per-block compute
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weight (262 ns) suggesting compute-bound — the per-core
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throughput drop from 2.69 (NEON-3) to 1.97 (NEON-4) confirms it.
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Same pattern as cycle 1 IDCT and cycle 2 LPF.
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Without a "no QPU" baseline in this bench (rerun with cycle 5's
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M3 alone gives 3.8 Mblock/s per core × 4 ≈ 15 Mblock/s
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theoretical), the same-kernel M4 verdict:
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- NEON-4 alone CDEF estimated ~9-10 Mblock/s (saturation
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reduces from theoretical 15 to actual; matches per-core 2.5
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trend)
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- NEON-3 + QPU CDEF (8.46) is **below NEON-4 alone**
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- Same-kernel M4: **NEGATIVE**
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This matches the pessimistic same-kernel-bench framing
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(`feedback_m4_same_kernel_worst_case.md`).
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### M4 mixed-kernel (deployment shape)
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| Config | CPU side | CPU agg | QPU CDEF |
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|---|---|---|---|
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| **NEON-3 MC + QPU CDEF** | MC | 34.17 Mblock/s | 0.424 Mblock/s |
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| **NEON-3 LPF4 + QPU CDEF** | LPF4 | 31.48 Medge/s | 0.414 Mblock/s |
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QPU CDEF contributes 0.41-0.42 Mblock/s while the CPU side runs
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near-maximum throughput. Compare against Issue 003 V1/V2
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NEON-fallback proxy (1.7 Mblock/s): the real QPU CDEF is
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~4× weaker than the NEON-on-core-3 proxy estimated, but still
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positive helper value.
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CPU MC agg in this mixed config (34.17 Mblock/s) is **higher**
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than CPU MC in Issue 003 V1 (24.49) — because the V1 proxy used
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NEON on core 3 which contended on the CPU memory bus, whereas
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the real QPU contends on the QPU side. Real-substrate-cross
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contention is gentler than NEON-core-3 proxy contention. **Issue
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003 V1/V2 numbers underestimated CPU side**, but correctly
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overestimated QPU helper magnitude.
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## Verdict
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| Rule | Result | Status |
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|---|---|---|
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| M1 bit-exact (3-way) | 100.00% on 4096 blocks | ✓ PASS |
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| R₅ = M2₅/M3₅ | 0.116 (ORANGE) | better than predicted |
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| M4 same-kernel | NEGATIVE (8.46 < ~10) | ✗ FAIL gate |
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| M4 mixed-kernel (CPU=MC) | +0.42 Mblock/s QPU helper | ✓ POSITIVE |
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| 30fps@1080p floor (isolation) | 0.46× | ✗ FAIL as sole substrate |
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| 30fps@1080p floor (CPU baseline) | 8.46 / 0.972 = 8.7× | ✓ PASS via CPU |
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**Engineering verdict**: CDEF QPU offload viable as
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**opportunistic helper**; CPU NEON remains primary substrate.
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Phase 8 V4L2 wrapper should expose CDEF QPU dispatch path, but
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scheduler defaults to CPU CDEF.
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**Surprise (positive)**: cycle 5 came in better than predicted
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(ORANGE not RED). The "compute-bound → QPU bad" classification
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held at the broad level, but the magnitude was less severe than
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extrapolated.
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## Deployment recipe update
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| Cycle | Kernel | Primary | QPU dispatch path | Verdict |
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|---|---|---|---|---|
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| 1 IDCT 8×8 | QPU | yes | M4 +7.2 % validated |
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| 2 LPF wd=4 | QPU | yes | M4 +6.9 % validated; V4 confirmed |
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| 3 MC 8h | CPU | exists, unused | QPU MC = 0.39 Mblock/s under any contention |
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| 4 LPF wd=8 | QPU | yes | M4 +4.1 % validated |
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| 5 CDEF | CPU | exists, opportunistic | QPU CDEF = 0.42 Mblock/s mixed, ~half-floor on its own |
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## Phase 9 lessons
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1. **Predictions extrapolated linearly from one cycle can be too
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pessimistic.** Cycle 3 MC R₃ = 0.067 extrapolated → R₅ = 0.02-0.05
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predicted; actual R₅ = 0.116. The "compute-bound" axis isn't a
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single dimension — CDEF and MC are both compute-bound but have
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different inner-loop shapes that affect V3D compiled code
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differently.
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2. **CDEF is bandwidth-bound on NEON despite high per-block ns.**
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Per-block 262 ns suggested "compute-bound" but per-core
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saturation at 4 cores (2.5 → 2.0 Mblock/s) shows the real
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constraint is memory bandwidth (192 u16 × 64 lanes/core reads
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+ 64 byte writes per block). This is a re-calibration of the
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bandwidth-bound/compute-bound classification: the binary
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categorization needs nuance.
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3. **Real-substrate-cross contention is gentler than same-side
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NEON proxy.** Issue 003 V1/V2 used NEON-on-core-3 as a "QPU
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helper" proxy; that overestimated the QPU's helper magnitude
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(because NEON-on-core-3 has more parallelism than QPU) but
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underestimated the CPU side throughput (because NEON-on-core-3
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contended on the CPU memory bus). The real QPU gives lower
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helper throughput but does NOT hurt the CPU side at all.
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4. **3-way M1 (QPU vs C ref vs NEON) caught nothing — but it would
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have caught the Phase 5 REDs cleanly.** The Phase 5 review's
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recommendation (YELLOW-1) was correct prudence; in this case
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the Phase 5 fixes prevented all bugs the gate would have caught,
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but the 3-way structure is the right discipline going forward.
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## What lands in this commit
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- `src/v3d_cdef.comp` (Phase 6 shader, 387 inst, 2 threads)
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- `tests/bench_v3d_cdef.c` (3-way M1, M2, R₅ classifier)
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- `tests/bench_concurrent_mixed.c` extended with K_CDEF on both
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sides; uses real QPU CDEF (Issue 003 NEON fallback removed)
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- `CMakeLists.txt`: build wiring for v3d_cdef.spv + bench_v3d_cdef
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- `docs/k5_cdef_phase7.md` (this doc) — Phase 7 closure
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- Memory: update `feedback_m4_same_kernel_worst_case.md` with
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cycle 5 real-QPU numbers (Issue 003 V1/V2 fallback proxy
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obsolete).
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