115 lines
3.3 KiB
Diff
115 lines
3.3 KiB
Diff
From: Markus Fritsche <mfritsche@reauktion.de>
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Subject: [PATCH] arm64: dts: rockchip: rk3399-pinebook-pro: extend OPP tables with OC entries (1.704 / 2.184 GHz)
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Inline the OPP-V2 cluster0 / cluster1 tables on the Pinebook Pro DTS to add
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overclock points: cluster0 (A53) up to 1.704 GHz @ 1.175 V, cluster1 (A72)
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up to 2.184 GHz @ 1.275 V.
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Original tables (from rk3399.dtsi → cluster0/1_opp) are reused intact for
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their points up to 1.416 / 1.800 GHz; the additional opp06 (cluster0) and
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opp08 (cluster1) extend the curve. Voltages above the stock max follow the
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community-validated PBP OC ladder; thermals on the Pinebook Pro chassis
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sustain these without throttling for normal workloads.
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The label match (`cluster0_opp`, `cluster1_opp`) means the DTC merges these
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inline tables with the parent ones rather than treating them as new nodes.
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opp00..opp05/07 have identical content to upstream; opp06/08 add the OC
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points.
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scope: board/pinebook-pro
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fleet: fresnel
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Signed-off-by: Markus Fritsche <mfritsche@reauktion.de>
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---
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arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 78 ++++++++++++++++++++
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1 file changed, 78 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
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--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
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@@ -18,6 +18,84 @@
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compatible = "pine64,pinebook-pro", "rockchip,rk3399";
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chassis-type = "laptop";
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+ cluster0_opp: opp-table-0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp00 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <750000 750000 1150000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp01 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <825000 825000 1150000>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <850000 850000 1150000>;
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+ };
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+ opp03 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <900000 900000 1150000>;
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+ };
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+ opp04 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <975000 975000 1150000>;
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+ };
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+ opp05 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <1100000 1100000 1150000>;
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+ };
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+ opp06 {
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+ opp-hz = /bits/ 64 <1704000000>;
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+ opp-microvolt = <1175000 1175000 1175000>;
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+ };
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+ };
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+
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+ cluster1_opp: opp-table-1 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp00 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <750000 750000 1250000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp01 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <800000 800000 1250000>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <825000 825000 1250000>;
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+ };
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+ opp03 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <850000 850000 1250000>;
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+ };
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+ opp04 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <900000 900000 1250000>;
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+ };
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+ opp05 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <975000 975000 1250000>;
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+ };
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+ opp06 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <1050000 1050000 1250000>;
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+ };
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+ opp07 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <1150000 1150000 1250000>;
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+ };
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+ opp08 {
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+ opp-hz = /bits/ 64 <2184000000>;
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+ opp-microvolt = <1275000 1275000 1275000>;
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+ };
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+ };
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+
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aliases {
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mmc0 = &sdio0;
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mmc1 = &sdmmc;
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