hwtest.c allocates BOs, builds the golden matmul regcmd with their real NPU
DMA addresses, patches in a bias BO, and submits to /dev/accel/accel0 on the
live mainline rocket kernel (boltzmann, 7.0.0-rc3-ARCH+).
Result: DRM_IOCTL_ROCKET_SUBMIT rc=0 (accepted) — the driver queues a job
built from our register buffer, coupling the Rosenblatt builder to real
silicon for the first time. Job does NOT complete (prep_bo -EBUSY, output
zero): the CNA weight path uses DCOMP decompression and we fed zeros, which
stalls the weight DMA. Completion needs real NPU-tiled/compressed weights
(rkt_coefs.c port) — next unit. No NPU hardware fault; cores stay bound; the
drm_mm_takedown WARN at fd-close is driver cleanup, not a hang.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
rkt_gemm_plan() partitions an MxN (full-K) output into <=tile_m x tile_n
sub-matmuls; rkt_gemm_op_fits() confirms a shape fits one rocket op via the
verified builder. First slice of the CPU+NPU backend: lets a gemma-scale GEMM
be expressed as many NPU ops. K-tiling (DPU partial-sum accumulation) deferred.
selftest: exact coverage of 64x200 by 8 tiles, every tile fits one op (K=64),
impossible-K reported unfit. Golden match unaffected. ALL PASS.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Adds userspace/npu-probe/verify/: a reference oracle built from Mesa's
UNMODIFIED rkt_task.c + rkt_regcmd.c (vendored, MIT) linked against a thin
shim (rkt_ml.h), which emits the ground-truth regcmd buffer for our test
matmul. 'make diff' byte-compares it against rkt_build_matmul_regcmd.
First run caught three real bugs, now fixed:
1. REG_DPU_RDMA_RDMA_S_POINTER emitted at target 0x1001, must be 0x2001
2. an 18-word CNA register run (CONV_CON2..FC_CON1) emitted twice
3. the whole DPU_RDMA block at 0x1001 instead of 0x2001 (EMIT_RDMA added)
Values were correct throughout; only block-targets and a copy-paste were
wrong. CNA stage rewritten to Mesa's single-pass order; coredpu RDMA regs
repointed. selftest histogram now counts the RDMA (0x2001) block.
Result: 130 words, IDENTICAL — GOLDEN MATCH. The builder is now proven, not
just faithful.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Ports Mesa rkt_task.c (fill_task + single-tile rkt_split_tasks branch) into
rkt_matmul.c so the declared public API is now real: a plain (M,N,K) GEMM is
mapped to a 1x1 conv and every low-level CNA/CORE/DPU field (banks, atomic
count, line/surface strides, data entries, kernel/channel alignment) is
derived from the NVDLA CBUF geometry (CBUF_BANKS=12, ENTRY=128, ATOMIC=16),
then handed to the two emit stages. Single-tile only: shapes needing CBUF
task-splitting return -1 rather than mis-emit.
selftest now drives the unified builder as the primary path; it produces a
buffer structurally identical to the hand-filled stage path (148 words, same
PC/CNA/CORE/DPU histogram) and refuses an oversized split-required shape.
Clean -Wall -Wextra, ALL PASS.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Makefile (make test / make lib) and selftest.c — a host-side smoke gate
for the CNA+CORE+DPU+PC regcmd builder. Not a golden-byte check (needs
Mesa/NPU); verifies the stages assemble without overflow, are
deterministic, report capacity exhaustion, and emit a sane per-block
target histogram. 148 words on a 4x8x16 single-tile GEMM, ALL PASS.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
rkt_matmul_coredpu.{c,h}: faithful port of Mesa rocket fill_first_regcmd's
CORE + DPU + PC sections (89 emits incl. float requant math via fui(), the
elementwise/add-tensor path, RDMA config, and the PC op-enable tail). Compiles
clean (-Wall -Wextra). Ported via the curl-driven dspark transformer (pi-run was
wedged on an MCP-connect hang) in 3 slices + hand-integrated the non-mechanical
spots (DMA addrs, float scales, raw emits, num_tasks/offset locals).
Builder now complete end to end: librocket + rkt_matmul_cna + rkt_matmul_coredpu
all build. Still faithful-to-Mesa, NOT golden-verified (needs Mesa build/NPU).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01EWpfhDgYNA21tETDP9ueBE
Phase-1 audit closes with a substantively different picture than the
original scaffold's TBDs:
- Tomeu Vizoso's RK3588 NPU work merged in Linux 6.18 (Nov 2025) under
codename `rocket` (NOT `rknpu`). All references updated.
- Boltzmann's `linux-rk3588-marfrit-A1` (7.0.0-rc3-ARCH+) already ships
`drivers/accel/rocket/rocket.ko` as a built-but-not-loaded module.
- DT bindings + per-core nodes (`npu@fdab/c/d_0000`,
compatible `rockchip,rk3588-rknn-core`) in mainline since 6.18 but
ship `status = "disabled"` — board enable is the Phase-2 unblock,
not a driver port.
- Mesa 25.3 ships Rocket Gallium + Teflon TFLite delegate as the
authoritative userspace reference for the uAPI shape.
- Op coverage today is conv-centric (MobileNet-class); transformer
matmul needs the conv-1×1 shoehorn (RKNPU2 BSP precedent) or rocket
op-set additions. Surfaced as Phase-2-load-bearing risk.
- IOMMU v1.0 hazard: 32 GB host needs `mem=4G` or local
`rockchip,rk3568-iommu-v1` discriminator patches before the first
NPU job, to avoid DMA-window faults.
Files:
- docs/npu-mainline-status.md: full audit table with upstream pointers
(kernel.org / Mesa docs / dri-devel patch URLs / Tomeu's "we are in
mainline" blog post).
- docs/phases.md: per-phase log entry for Phase-1 closeout.
- docs/op-coverage.md: matmul-vs-conv-vs-rocket-op-set framing.
- fleet/boltzmann.yaml: audited kernel + npu_driver + dt_npu_nodes
state.
- kernel/dt-overlays/rk3588-rosenblatt-npu-enable.dtso: overlay to
flip the three rknn-core nodes to "okay" (+ matching mmu nodes),
carries the IOMMU-mitigation warning inline.
- kernel/README.md: kernel-agent scope wiring + anticipated local
carry patches.
- README.md: phase-status table + "rknpu → rocket" rename note.
- TODO.md: Phase-2 unblock concrete steps + standing
upstream-watch items.
Codename: Frank Rosenblatt — Mark I Perceptron 1958, the first
hardware neural network. This project lights up the RK3588 NPU on
mainline Linux so the OSS world finally owns the silicon-side of
inference on that chip.
Phase-1 scope: small LLM running CPU + NPU mix on boltzmann (Rock 5
ITX+). Backend: llama.cpp with a new rknpu ggml backend offloading
INT8 GEMM (attention + FFN matmuls) to the NPU's tile-MAC array while
leaving dequant / RoPE / softmax / sampling / embedding on A76 NEON.
Target model: qwen2.5-1.5B-instruct Q4_K_M GGUF.
Scaffold layout: README.md (frame + 9+1-phase plan), TODO.md (rolling
punch-list), docs/{npu-mainline-status,architecture}.md, kernel/ for
DT bindings + driver tweaks, userspace/{npu-probe,llm-runtime}/,
fleet/boltzmann.yaml.
Next: Phase-1 substrate audit — fill the TBDs in docs/npu-mainline-status.md
with the actual state of Tomeu Vizoso's rknpu / DRM-accel work on
the boltzmann-running kernel.
Markus Fritsche
marfrit